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From: Stanimir Varbanov <svarbanov@suse.de>
To: Jim Quinlan <james.quinlan@broadcom.com>,
	linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls
Date: Mon, 15 Jul 2024 17:01:18 +0300	[thread overview]
Message-ID: <dd95d25c-4bea-4019-a5e4-e68f359516ef@suse.de> (raw)
In-Reply-To: <20240710221630.29561-11-james.quinlan@broadcom.com>



On 7/11/24 01:16, Jim Quinlan wrote:
> In some cases the result of a reset_control_xxx() call have been ignored.
> Now we check all return values of such functions and propagate the error to
> the next level.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 100 ++++++++++++++++++--------
>  1 file changed, 71 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index c44a92217855..c334cc427fb7 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -232,8 +232,8 @@ struct pcie_cfg_data {
>  	const enum pcie_type type;
>  	const bool has_phy;
>  	unsigned int num_inbound;
> -	void (*perst_set)(struct brcm_pcie *pcie, u32 val);
> -	void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
> +	int (*perst_set)(struct brcm_pcie *pcie, u32 val);
> +	int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
>  };
>  
>  struct subdev_regulators {
> @@ -278,8 +278,8 @@ struct brcm_pcie {
>  	int			num_memc;
>  	u64			memc_size[PCIE_BRCM_MAX_MEMC];
>  	u32			hw_rev;
> -	void			(*perst_set)(struct brcm_pcie *pcie, u32 val);
> -	void			(*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
> +	int			(*perst_set)(struct brcm_pcie *pcie, u32 val);
> +	int			(*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
>  	struct subdev_regulators *sr;
>  	bool			ep_wakeup_capable;
>  	bool			has_phy;
> @@ -742,13 +742,18 @@ static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
>  	return base + DATA_ADDR(pcie);
>  }
>  
> -static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
> +static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
>  {
> +	int ret = 0;
> +
>  	if (pcie->bridge) {
>  		if (val)
> -			reset_control_assert(pcie->bridge);
> +			ret = reset_control_assert(pcie->bridge);
>  		else
> -			reset_control_deassert(pcie->bridge);
> +			ret = reset_control_deassert(pcie->bridge);
> +		if (ret)
> +			dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n",
> +				val ? "assert" : "deassert", ret);
>  	} else {
>  		u32 tmp, mask =  RGR1_SW_INIT_1_INIT_GENERIC_MASK;
>  		u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
> @@ -757,9 +762,10 @@ static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val
>  		tmp = (tmp & ~mask) | ((val << shift) & mask);
>  		writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
>  	}

In case you sending new version, please add a blank like here.

Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>

~Stan

> +	return ret;
>  }
>  

  reply	other threads:[~2024-07-15 14:01 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-10 22:16 [PATCH v3 00/12] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-07-10 22:16 ` [PATCH v3 01/12] dt-bindings: PCI: Change brcmstb YAML maintainer Jim Quinlan
2024-07-11 21:24   ` Rob Herring (Arm)
2024-07-14 20:18   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 02/12] dt-bindings: PCI: Cleanup of brcmstb YAML and add 7712 SoC Jim Quinlan
2024-07-11  6:21   ` Krzysztof Kozlowski
2024-07-10 22:16 ` [PATCH v3 03/12] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-07-15 10:32   ` Stanimir Varbanov
2024-07-15 21:10   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 04/12] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-13 19:12   ` Amit Singh Tomar
2024-07-16 18:40     ` Jim Quinlan
2024-07-16 19:06       ` Amit Singh Tomar
2024-07-15 10:33   ` Stanimir Varbanov
2024-07-15 21:10   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 05/12] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-15 10:35   ` Stanimir Varbanov
2024-07-15 21:09   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 06/12] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-07-15 10:36   ` Stanimir Varbanov
2024-07-15 21:09   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 07/12] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 08/12] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 09/12] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-07-15 10:38   ` Stanimir Varbanov
2024-07-10 22:16 ` [PATCH v3 10/12] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-07-15 14:01   ` Stanimir Varbanov [this message]
2024-07-15 21:08   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 11/12] PCI: brcmstb: Change field name from 'type' to 'model' Jim Quinlan
2024-07-15 21:06   ` Florian Fainelli
2024-07-10 22:16 ` [PATCH v3 12/12] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan
2024-07-15 21:12   ` Florian Fainelli
2024-07-14 20:15 ` [PATCH v3 00/12] PCI: brcnstb: Enable STB 7712 SOC Florian Fainelli
2024-07-15 17:24 ` Florian Fainelli

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