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Thu, 18 Jul 2024 06:43:43 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46I6hhOH004524 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 18 Jul 2024 06:43:43 GMT Received: from [10.151.37.100] (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 17 Jul 2024 23:43:37 -0700 Message-ID: Date: Thu, 18 Jul 2024 12:13:34 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V6 4/4] PCI: qcom: Add support for IPQ9574 To: Manivannan Sadhasivam CC: , , , , , , , , , , , , devi priya , Dmitry Baryshkov , Manivannan Sadhasivam , Anusha Rao References: <20240716092347.2177153-1-quic_srichara@quicinc.com> <20240716092347.2177153-5-quic_srichara@quicinc.com> <20240717083856.GD2574@thinkpad> Content-Language: en-US From: Sricharan Ramabadhran In-Reply-To: <20240717083856.GD2574@thinkpad> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: ufqeYTtQOUeouqgZUXXrvP064jfAI_zQ X-Proofpoint-ORIG-GUID: ufqeYTtQOUeouqgZUXXrvP064jfAI_zQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-18_03,2024-07-17_02,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 spamscore=0 mlxscore=0 bulkscore=0 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 clxscore=1015 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407180044 On 7/17/2024 2:08 PM, Manivannan Sadhasivam wrote: > On Tue, Jul 16, 2024 at 02:53:47PM +0530, Sricharan R wrote: >> From: devi priya >> >> The IPQ9574 platform has four Gen3 PCIe controllers: >> two single-lane and two dual-lane based on SNPS core 5.70a. >> >> QCOM IP rev is 1.27.0 and Synopsys IP rev is 5.80a. >> Add a new compatible 'qcom,pcie-ipq9574' and 'ops_1_27_0' >> which reuses all the members of 'ops_2_9_0' except for the >> post_init as the SLV_ADDR_SPACE_SIZE configuration differs >> between 2_9_0 and 1_27_0. >> >> Reviewed-by: Dmitry Baryshkov >> Reviewed-by: Manivannan Sadhasivam >> Co-developed-by: Anusha Rao >> Signed-off-by: Anusha Rao >> Signed-off-by: devi priya >> Signed-off-by: Sricharan Ramabadhran >> --- >> [V6] Fixed all Manivannan's and Bjorn Helgaas comments. >> Removed the SLV_ADDR_SPACE_SZ_1_27_0 macro to have default value. >> >> drivers/pci/controller/dwc/pcie-qcom.c | 31 ++++++++++++++++++++++---- >> 1 file changed, 27 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c >> index 0180edf3310e..26acd9f5385e 100644 >> --- a/drivers/pci/controller/dwc/pcie-qcom.c >> +++ b/drivers/pci/controller/dwc/pcie-qcom.c >> @@ -1116,16 +1116,13 @@ static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) >> return clk_bulk_prepare_enable(res->num_clks, res->clks); >> } >> >> -static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> +static int qcom_pcie_post_init(struct qcom_pcie *pcie) >> { >> struct dw_pcie *pci = pcie->pci; >> u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); >> u32 val; >> int i; >> >> - writel(SLV_ADDR_SPACE_SZ, >> - pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); >> - >> val = readl(pcie->parf + PARF_PHY_CTRL); >> val &= ~PHY_TEST_PWR_DOWN; >> writel(val, pcie->parf + PARF_PHY_CTRL); >> @@ -1165,6 +1162,18 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> return 0; >> } >> >> +static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) >> +{ >> + return qcom_pcie_post_init(pcie); >> +} >> + >> +static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) >> +{ >> + writel(SLV_ADDR_SPACE_SZ, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE); >> + > As discussed in [1], DBI/ATU mirroring should be disabled completely to avoid > the enumeration issue you are seeing on this platform. Please rebase on top of > the referenced patch (once v2 gets posted). ok, got it. Regards,  Sricharan