[PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Jim Quinlan]

This series enables a new SoC to run with the existing Brcm STB PCIe
driver.  Previous chips all required that an inbound window have a size
that is a power of two; this chip, and next generations chips like it, can
have windows of any reasonable size.

Note: This series must follow the commits of two previous and pending
      series [1,2].

[1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
[2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/

Jim Quinlan (3):
  dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC
  PCI: brcmstb: Acommodate newer SOCs with next-gen PCIe inbound mapping
  PCI: brcmstb: Add 74110a0 SoC configuration details

 .../bindings/pci/brcm,stb-pcie.yaml           |  1 +
 drivers/pci/controller/pcie-brcmstb.c         | 80 ++++++++++++++++++-
 2 files changed, 80 insertions(+), 1 deletion(-)


base-commit: 17bbde2e1716e2ee4b997d476b48ae85c5a47671
prerequisite-patch-id: 82aa80f7ebaa1ee1d48b59bd7f1eb6b21db3c41d
prerequisite-patch-id: e7b6b6e618ee225c9f4892a6078e7b3c4f8b1c73
prerequisite-patch-id: 66cabe0efb02132ce7cf8a849b5bb7f19ab407a2
prerequisite-patch-id: 118fda1b363bc18ef0736f917d1dd5497699156e
prerequisite-patch-id: a48573e6eca090a032c0932ff89f26eae4162db8
-- 
2.34.1

[PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Jim Quinlan]

Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
inbound window may be set to any size, unlike previous STB
SoCs whose inbound window size must be a power of two.

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index 5a7b0ed9464d..36bebc290b42 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -27,6 +27,7 @@ properties:
           - brcm,bcm7445-pcie # Broadcom 7445 Arm
           - brcm,bcm7712-pcie # Broadcom STB sibling of Rpi 5
           - brcm,bcm33940-pcie # Broadcom DOCSIS 4.0 CM w/ 64b ARM
+          - brcm,bcm74110-pcie # Broadcom STB, Arm64
 
   reg:
     maxItems: 1
-- 
2.34.1

[PATCH 2/3] PCI: brcmstb: Acommodate newer SOCs with next-gen PCIe inbound mapping

[Jim Quinlan]

New SoCs are coming that are not encumbered with a baroque internal memory
mapping scheme or power-of-two restrictions on the sizes of inbound
regsions.  Enable the driver to use these SoCs.

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 61 ++++++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5c8aa5e36338..362ac083e112 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -152,6 +152,8 @@
 
 #define PCIE_MSI_INTR2_BASE		0x4500
 
+#define PCIE_MISC2_BAR1_CONFIG_SIZE				0x4700
+
 /* Offsets from INTR2_CPU and MSI_INTR2 BASE offsets */
 #define  MSI_INT_STATUS			0x0
 #define  MSI_INT_CLR			0x8
@@ -282,6 +284,15 @@ enum pcie_soc_base {
  */
 #define IS_CM_SOC(t) ((t) == BCM3162 || (t) == BCM33940 || (t) == BCM3392)
 
+/*
+ * Newer chips (NG is "Next Generation") have simplified the design of how
+ * inbound regions are mapped to system memory as compared to previous STB
+ * designs.  In addition, the inbound window size is not restricted to be a
+ * power of two.  Such systems may or may not have an IOMMU between the RC
+ * and memory.
+ */
+#define IS_NG_PCI_SOC(t) (0)
+
 struct inbound_win {
 	u64 size;
 	u64 pci_offset;
@@ -1008,7 +1019,8 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
 		 * memory.  That being said, each window's size must still
 		 * be a power of two.
 		 */
-		if (pcie->cfg->soc_base == BCM7712 || IS_CM_SOC(pcie->cfg->soc_base))
+		if (pcie->cfg->soc_base == BCM7712 || IS_CM_SOC(pcie->cfg->soc_base)
+		    || IS_NG_PCI_SOC(pcie->cfg->soc_base))
 			add_inbound_win(b++, &n, size, cpu_start, pcie_start);
 
 		if (n > pcie->cfg->num_inbound_wins)
@@ -1020,6 +1032,22 @@ static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie,
 		return -EINVAL;
 	}
 
+	if (IS_NG_PCI_SOC(pcie->cfg->soc_base)) {
+		/*
+		 * STB NG SoCs may still be limited with three inbound
+		 * windows, and if so, the last one should be disabled.
+		 */
+		if (pcie->cfg->num_inbound_wins == 3) {
+			n = 2;
+			add_inbound_win(b++, &n, 0, 0, 0);
+		}
+		/*
+		 * NG SoCs do not have internal mapping system that enables
+		 * multiple memory controllers, so return now.
+		 */
+		return n;
+	}
+
 	/*
 	 * 7712, CM, and newer chips do not have an internal memory
 	 * mapping system that enables multiple memory controllers.  As
@@ -1120,6 +1148,17 @@ static u32 brcm_ubus_reg_offset(int bar)
 		return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4);
 }
 
+/*
+ * NG SoCs have configurable inbound region size registers (as opposed to
+ * having to set them to a power of two).  There are multiple contiguous
+ * registers, one for each inbound window.  This function provides the
+ * register offset for a specific window.
+ */
+static unsigned int brcm_calc_config_size_reg_offset(int bar)
+{
+	return PCIE_MISC2_BAR1_CONFIG_SIZE + (bar - 1) * 4;
+}
+
 static void set_inbound_win_registers(struct brcm_pcie *pcie,
 				      const struct inbound_win *inbound_wins,
 				      u8 num_inbound_wins)
@@ -1134,6 +1173,24 @@ static void set_inbound_win_registers(struct brcm_pcie *pcie,
 		u32 reg_offset = brcm_bar_reg_offset(i);
 		u32 tmp = lower_32_bits(pci_offset);
 
+		if (IS_NG_PCI_SOC(pcie->cfg->soc_base)) {
+			/* PCIe address */
+			writel(lower_32_bits(pci_offset), base + reg_offset);
+			writel(upper_32_bits(pci_offset), base + reg_offset + 4);
+
+			/* Size of region */
+			reg_offset = brcm_calc_config_size_reg_offset(i);
+			/* Register value has granularity of 4k units */
+			writel(size >> 12, base + reg_offset);
+
+			/* CPU address */
+			reg_offset = brcm_ubus_reg_offset(i);
+			writel(lower_32_bits(cpu_addr), base + reg_offset);
+			writel(upper_32_bits(cpu_addr), base + reg_offset + 4);
+
+			continue;
+		}
+
 		u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(size),
 				  PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK);
 
@@ -1264,6 +1321,8 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
 	 */
 	if (IS_CM_SOC(pcie->cfg->soc_base))
 		pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_FOR_CM;
+	else if (IS_NG_PCI_SOC(pcie->cfg->soc_base))
+		pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
 	else if (inbound_wins[2].pci_offset >= SZ_4G ||
 		 (inbound_wins[2].size + inbound_wins[2].pci_offset) < SZ_4G)
 		pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
-- 
2.34.1

[PATCH 3/3] PCI: brcmstb: Add 74110a0 SoC configuration details

[Jim Quinlan]

Enable PCIe for 74110a0 SoC.  This chip uses a simple mechanism
to map inbound memory regions.  Both the "ranges" and "dma-ranges"
are identity-mapped to PCIe space.

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
---
 drivers/pci/controller/pcie-brcmstb.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 362ac083e112..bfedab15a162 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -276,6 +276,7 @@ enum pcie_soc_base {
 	BCM7435,
 	BCM7712,
 	BCM33940,
+	BCM74110,
 };
 
 /*
@@ -291,7 +292,7 @@ enum pcie_soc_base {
  * power of two.  Such systems may or may not have an IOMMU between the RC
  * and memory.
  */
-#define IS_NG_PCI_SOC(t) (0)
+#define IS_NG_PCI_SOC(t) ((t) == BCM74110)
 
 struct inbound_win {
 	u64 size;
@@ -2046,6 +2047,14 @@ static const int pcie_offsets_bcm7712[] = {
 	[PCIE_INTR2_CPU_BASE]	= 0x4400,
 };
 
+static const int pcie_offset_bcm74110[] = {
+	[RGR1_SW_INIT_1] = 0xc010,
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x8000,
+	[PCIE_HARD_DEBUG] = 0x4204,
+	[PCIE_INTR2_CPU_BASE] = 0x4300,
+};
+
 static const int pcie_offset_bcm33940[] = {
 	[RGR1_SW_INIT_1] = 0x9210,
 	[EXT_CFG_INDEX] = 0x9000,
@@ -2162,6 +2171,15 @@ static const struct pcie_cfg_data bcm33940_cfg = {
 	.num_inbound_wins = 10,
 };
 
+static const struct pcie_cfg_data bcm74110_cfg = {
+	.offsets	= pcie_offset_bcm74110,
+	.soc_base	= BCM74110,
+	.perst_set	= brcm_pcie_perst_set_7278,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+	.has_phy	= true,
+	.has_err_report	= true,
+};
+
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
 	{ .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
@@ -2177,6 +2195,7 @@ static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
 	{ .compatible = "brcm,bcm33940-pcie", .data = &bcm33940_cfg },
+	{ .compatible = "brcm,bcm74110-pcie", .data = &bcm74110_cfg },
 	{},
 };
 
-- 
2.34.1

Re: [PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Florian Fainelli]

On 7/3/2025 2:53 PM, Jim Quinlan wrote:
> Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
> inbound window may be set to any size, unlike previous STB
> SoCs whose inbound window size must be a power of two.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [PATCH 2/3] PCI: brcmstb: Acommodate newer SOCs with next-gen PCIe inbound mapping

[Florian Fainelli]

On 7/3/2025 2:53 PM, Jim Quinlan wrote:
> New SoCs are coming that are not encumbered with a baroque internal memory
> mapping scheme or power-of-two restrictions on the sizes of inbound
> regsions.  Enable the driver to use these SoCs.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [PATCH 3/3] PCI: brcmstb: Add 74110a0 SoC configuration details

[Florian Fainelli]

On 7/3/2025 2:53 PM, Jim Quinlan wrote:
> Enable PCIe for 74110a0 SoC.  This chip uses a simple mechanism
> to map inbound memory regions.  Both the "ranges" and "dma-ranges"
> are identity-mapped to PCIe space.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>

> ---
>   drivers/pci/controller/pcie-brcmstb.c | 21 ++++++++++++++++++++-
>   1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 362ac083e112..bfedab15a162 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -276,6 +276,7 @@ enum pcie_soc_base {
>   	BCM7435,
>   	BCM7712,
>   	BCM33940,
> +	BCM74110,
>   };
>   
>   /*
> @@ -291,7 +292,7 @@ enum pcie_soc_base {
>    * power of two.  Such systems may or may not have an IOMMU between the RC
>    * and memory.
>    */
> -#define IS_NG_PCI_SOC(t) (0)
> +#define IS_NG_PCI_SOC(t) ((t) == BCM74110)
>   
>   struct inbound_win {
>   	u64 size;
> @@ -2046,6 +2047,14 @@ static const int pcie_offsets_bcm7712[] = {
>   	[PCIE_INTR2_CPU_BASE]	= 0x4400,
>   };
>   
> +static const int pcie_offset_bcm74110[] = {
> +	[RGR1_SW_INIT_1] = 0xc010,
> +	[EXT_CFG_INDEX]  = 0x9000,
> +	[EXT_CFG_DATA]   = 0x8000,
> +	[PCIE_HARD_DEBUG] = 0x4204,
> +	[PCIE_INTR2_CPU_BASE] = 0x4300,
> +};
> +
>   static const int pcie_offset_bcm33940[] = {
>   	[RGR1_SW_INIT_1] = 0x9210,
>   	[EXT_CFG_INDEX] = 0x9000,
> @@ -2162,6 +2171,15 @@ static const struct pcie_cfg_data bcm33940_cfg = {
>   	.num_inbound_wins = 10,
>   };
>   
> +static const struct pcie_cfg_data bcm74110_cfg = {
> +	.offsets	= pcie_offset_bcm74110,
> +	.soc_base	= BCM74110,
> +	.perst_set	= brcm_pcie_perst_set_7278,
> +	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
> +	.has_phy	= true,
> +	.has_err_report	= true,
> +};
> +
>   static const struct of_device_id brcm_pcie_match[] = {
>   	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
>   	{ .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
> @@ -2177,6 +2195,7 @@ static const struct of_device_id brcm_pcie_match[] = {
>   	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
>   	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
>   	{ .compatible = "brcm,bcm33940-pcie", .data = &bcm33940_cfg },
> +	{ .compatible = "brcm,bcm74110-pcie", .data = &bcm74110_cfg },

Nit: if you need to respin, it might be nice to order numerically here?
-- 
Florian

Re: [PATCH 1/3] dt-bindings: PCI: brcm,stb-pcie: Add 74110 SoC

[Rob Herring (Arm)]

On Thu, 03 Jul 2025 17:53:11 -0400, Jim Quinlan wrote:
> Adds BCM74110, a Broadcom SetTop box ARM64 based SoC.  Its
> inbound window may be set to any size, unlike previous STB
> SoCs whose inbound window size must be a power of two.
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
>  Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Manivannan Sadhasivam]

On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> This series enables a new SoC to run with the existing Brcm STB PCIe
> driver.  Previous chips all required that an inbound window have a size
> that is a power of two; this chip, and next generations chips like it, can
> have windows of any reasonable size.
> 
> Note: This series must follow the commits of two previous and pending
>       series [1,2].
> 
> [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/

Have you considered my comment on this series?
https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/

- Mani

-- 
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Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Jim Quinlan]

[-- Attachment #1: Type: text/plain, Size: 1682 bytes --]

On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
>
> On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> > This series enables a new SoC to run with the existing Brcm STB PCIe
> > driver.  Previous chips all required that an inbound window have a size
> > that is a power of two; this chip, and next generations chips like it, can
> > have windows of any reasonable size.
> >
> > Note: This series must follow the commits of two previous and pending
> >       series [1,2].
> >
> > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/
>
> Have you considered my comment on this series?
> https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/

Hi Mani,
I'm sorry, I thought I replied to this but obviously I did not.

Your points are valid.  Our PCIe HW block keeps on mutating, and each
time it does we add new code that is triggered off of the soc_base
config setting.  The end result is not easy on the eyes.

I  also have submitted the series "PCI: brcmstb: Include cable-modem
SoCs".  I don't think it has review comments yet, but I am guessing
that you will make the same points.

So it looks like what you are asking for is a refactoring of the
driver and, AFAICT, I need to first submit separate series that does
this before submitting the this and the cable modem submission.  Do
you agree with that?

Regards,
Jim Quinlan
Broadcom STB/CM


>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்

[-- Attachment #2: S/MIME Cryptographic Signature --]
[-- Type: application/pkcs7-signature, Size: 4197 bytes --]

Re: [PATCH 0/3] PCI: brcmstb: Add 74110a0 SoC configuration

[Manivannan Sadhasivam]

On Wed, Aug 20, 2025 at 01:08:41PM GMT, Jim Quinlan wrote:
> On Tue, Aug 19, 2025 at 10:51 AM Manivannan Sadhasivam <mani@kernel.org> wrote:
> >
> > On Thu, Jul 03, 2025 at 05:53:10PM GMT, Jim Quinlan wrote:
> > > This series enables a new SoC to run with the existing Brcm STB PCIe
> > > driver.  Previous chips all required that an inbound window have a size
> > > that is a power of two; this chip, and next generations chips like it, can
> > > have windows of any reasonable size.
> > >
> > > Note: This series must follow the commits of two previous and pending
> > >       series [1,2].
> > >
> > > [1] https://lore.kernel.org/linux-pci/20250613220843.698227-1-james.quinlan@broadcom.com/
> > > [2] https://lore.kernel.org/linux-pci/20250609221710.10315-1-james.quinlan@broadcom.com/
> >
> > Have you considered my comment on this series?
> > https://lore.kernel.org/linux-pci/a2ebnh3hmcbd5zr545cwu7bcbv6xbhvv7qnsjzovqbkar5apak@kviufeyk5ssr/
> 
> Hi Mani,
> I'm sorry, I thought I replied to this but obviously I did not.
> 

No issues!

> Your points are valid.  Our PCIe HW block keeps on mutating, and each
> time it does we add new code that is triggered off of the soc_base
> config setting.  The end result is not easy on the eyes.
> 
> I  also have submitted the series "PCI: brcmstb: Include cable-modem
> SoCs".  I don't think it has review comments yet, but I am guessing
> that you will make the same points.
> 

Yes. I intentionally didn't give any comments or merge it since I have the same
refactoring comments.

> So it looks like what you are asking for is a refactoring of the
> driver and, AFAICT, I need to first submit separate series that does
> this before submitting the this and the cable modem submission.  Do
> you agree with that?
> 

Yes, I agree. Refactoring will make life easier for both you and me :)

- Mani

-- 
மணிவண்ணன் சதாசிவம்