From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 345A2192D9D; Fri, 25 Apr 2025 16:24:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745598277; cv=none; b=A/uvZFB53z6QynSWOUOLdNdn1SYbKOcipB0dGX9KSYfyXO4T6/0KP3QC0dGiPgqvu+NJwwxmmh/1isfjZjPKw+N2n3Yx3v1mvEKOHr15Z9BzBPgPQyMC0HgkjnsJo5dxZ8f91Bm/ItzgKNh2CWCYl2lVea3q9xwoUjoZkHB7M6U= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745598277; c=relaxed/simple; bh=0GFMS3oQO3Rfhk5zSJVgp9cNKNXDLQ3zkyosWiK6rY0=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=YkNxCuY/qmdBfTQtv5lV1BNHmItzPum968PRwE5e1t/WvGMzPxyW4/v7PZUqYSQ8vc6H/mJkt9uCB0z2AuGgHFU94OXm41GZ0CMYJnrySISTTTiXVsew/HVP2SGQvuAGLvJXEUVgbCRHuWOwcZYM3NLYvncPcSxn4LW5ToTMMuE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h87yuawY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h87yuawY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC211C4CEE4; Fri, 25 Apr 2025 16:24:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745598276; bh=0GFMS3oQO3Rfhk5zSJVgp9cNKNXDLQ3zkyosWiK6rY0=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=h87yuawYT+EKcR4ArMVXNZPbEuY1HCk3rkbmyoVXdv8miu/hBa40JymGrA6n/zVA/ OeQKiPxNJoEhMD5LWcHT2EG3rRa9aDYVXlRarAAiwuLLEKDGP4OYOb0dmZbLXWc2oj Wh0UWtMQmerqCAZ63G5s00LxsBfoBt0xMC7yPwsVAt9fhGyrbB94mn9XU4sZ6J2b1X oArEu7niQa+jMcBtHp1h+hP9dE8iqXsSEUT9GQhuBIpgpmozvxXNthD+DSvNUT2Sws X554GUKukZ1gr1f94Mr3NA5YP2k/6kozZZpHDWOz2s3MJCvDAXNsPpfA7nlSdhWh7D V3MOroidqWlaw== Message-ID: Date: Fri, 25 Apr 2025 18:24:32 +0200 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/5] Enhance the PCIe controller driver To: hans.zhang@cixtech.com, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: peter.chen@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250424010445.2260090-1-hans.zhang@cixtech.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 24/04/2025 03:04, hans.zhang@cixtech.com wrote: > From: Hans Zhang > > Enhances the exiting Cadence PCIe controller drivers to support > HPA (High Performance Architecture) Cadence PCIe controllers. > > The patch set enhances the Cadence PCIe driver for HPA support. > The "compatible" property in DTS is added with more enum to support > the new platform architecture and the register maps that change with > it. The driver read register and write register functions take the > updated offset stored from the platform driver to access the registers. > The driver now supports the legacy and HPA architecture, with the > legacy code changes beingminimal. > > SoC related changes are not available in this patch set. > > The TI SoC continues to be supported with the changes incorporated. > > The changes are also in tune with how multiple platforms are supported > in related drivers. > > The scripts/checkpatch.pl has been run on the patches with and without > --strict. With the --strict option, 4 checks are generated on 1 patch > (PATCH v3 3/6) of the series), which can be ignored. There are no code > fixes required for these checks. The rest of the 'scripts/checkpatch.pl' > is clean. > > The ./scripts/kernel-doc --none have been run on the changed files. > > The changes are tested on TI platforms. The legacy controller changes are > tested on an TI J7200 EVM and HPA changes are planned for on an FPGA > platform available within Cadence. > > Changes for v4 > - Add header file bitfield.h to pcie-cadence.h. > - Addressed the following review comments. > Merged the TI patch as it. > Removed initialization of struct variables to '0'. So the rest you did not address? That's not acceptable. You ignored several comments such way. Either discussion did not finish or you agree to implement all comments. If you do not agree, then sending new version hides the previous discussion. Best regards, Krzysztof