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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: MzPqexjToSm6FAFJbQKCngQlFX_4lW-i X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIxMDEwOCBTYWx0ZWRfX21+IzW9p399K LwSw5ukQsAmt33sEkZkfL9neeT0DGlZ98i6aNNKnnR1DXKUEmVXeHWeXVSy8X2g+gzfiZQaVvZ+ giw1D31/Bje9TzFttKjuvmqztTcqVMMFjvL2VcldO4VcgHDwfdyt8Q3qveZR29YukA7X+9Fp6aq udNlEibuZOBd8vJ5Rv9OKzhE4d/ChYEdeItrrKRnCO54kRRxvp1zHX25ZA+9nwOSZRvtA4jMWhd A0aJu8zak+J2bvFFZaN/fRJN3I2TbCe7YysrxAiT9Iqhr2Lno7CZiAW18cra9L3m6MTW4xZ+Nn2 p0BguvnQv/T+UV6W/p+nI9bcSLQvaz6KUCheuwoQ4bjkyFZC7VlTrZzfCci23Y3ibQ9RVb5tvuq Xo1QRMsQi9yNGw/7ie0cLUUhjsxnMGsycQA820wafNEwa3gooHDRxQgpAIp2sqjkAK/6w36plp0 h5QJRJBbfyp33t9BWXQ== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIxMDEwOCBTYWx0ZWRfX0n+oBzHI4J/Y c7ACzMwvqs1wqDRkF6Q1LIEHdoMq0L2Hmdl1Gm+ImI/RjAUAzmYVMV54JbIbnPiiwxYw+ARegNS Ii0REQ/CWioj7b+NpeJn/dt7M28g0wc= X-Authority-Analysis: v=2.4 cv=BKAmP1QG c=1 sm=1 tr=0 ts=6ab0deb2 cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=eQCDFL0YdFa3ysEWRUMA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-GUID: MzPqexjToSm6FAFJbQKCngQlFX_4lW-i X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_03,2026-09-16_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 suspectscore=0 impostorscore=0 spamscore=0 malwarescore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609210108 On 9/21/26 8:30 AM, Qiang Yu wrote: > On Mon, Sep 21, 2026 at 11:07:08AM +0530, Krishna Chaitanya Chundru wrote: >> This series adds PCIe support for the Qualcomm Nord (SA8797P) platform. >> >> Nord has a single Gen5-capable QMP PCIe PHY block split into four >> independently-clocked and independently-resettable ports (A/B/C/D). >> Firmware selects the active lane topology at boot via a TCSR >> configuration register, and the same PHY block can appear as a single >> x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This >> is similar in spirit to the Glymur multi-PHY support already posted, >> except Nord's PHY registers are programmed by Linux rather than by >> firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init >> tables along with the power-up/power-down/soft-reset sequencing needed >> to bring each port up. >> >> The series also documents and wires up the qcom,nord-pcie compatible >> (reusing the existing SA8775P PCIe controller binding), and adds a >> CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing >> convergence issue in the PCIe power domain. >> >> Signed-off-by: Krishna Chaitanya Chundru > > Tested on Glymur CRD and Glymur QCB, devices can be enumerated. A test of "this didn't break my completely different board" is welcome, but looks a little confusing without you saying that was the intent specifically - unless maybe it wasn't? Konrad