From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9FA2CC31E49 for ; Wed, 19 Jun 2019 03:56:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6321A2084B for ; Wed, 19 Jun 2019 03:56:30 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="Bmvrxy4T" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729356AbfFSD43 (ORCPT ); Tue, 18 Jun 2019 23:56:29 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:14842 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728195AbfFSD43 (ORCPT ); Tue, 18 Jun 2019 23:56:29 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 18 Jun 2019 20:56:26 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 18 Jun 2019 20:56:26 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 20:56:26 -0700 Received: from [10.24.192.29] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 19 Jun 2019 03:56:23 +0000 Subject: Re: [PATCH V6 20/27] PCI: tegra: Disable MSI for Tegra PCIe root port To: Bjorn Helgaas CC: , , , , , , , , References: <20190618180206.4908-1-mmaddireddy@nvidia.com> <20190618180206.4908-21-mmaddireddy@nvidia.com> <20190618194830.GA110859@google.com> X-Nvconfidentiality: public From: Manikanta Maddireddy Message-ID: Date: Wed, 19 Jun 2019 09:25:54 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 In-Reply-To: <20190618194830.GA110859@google.com> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Language: en-US DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1560916586; bh=4JstVY89KTv+Xb8i7slBmq/+fO6Mvwf3ij94+ExbInI=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type: Content-Transfer-Encoding:Content-Language; b=Bmvrxy4T7vbdnMZSgVZC9KVFU7iUyru5X4Uf4a33CZY42bCc6WQm4WzKkDEiPPdVT 7WMb8tavi7AkvANKRzJLnNAhuNelJrjWQbYArMS/9y32nmIdokw89cLsnNYqJCEcel 56s4oxttrVFYuXEYCYwXRRQ3WO0j2mn6abh5F+GkjGXWrHCudL8mT9vkwGbRmcRPxv zTHAOOEDsY7KYYedOLBTewXGLXR+fKKepa8PGYpoI/0IUtIpJswg+p1QEfmcrmqaai hA4vH7akZ7I2FM26FDOBQ+QJYwbs86Mm77oIWuxiyGdiSi7GXAG50qNZDgiuKhD3Dp 3XULOPXsIywFA== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 19-Jun-19 1:18 AM, Bjorn Helgaas wrote: > On Tue, Jun 18, 2019 at 11:31:59PM +0530, Manikanta Maddireddy wrote: >> Tegra PCIe generates PME and AER events over legacy interrupt line. Disable >> MSI to avoid service drivers registering interrupt routine over MSI IRQ >> line. >> >> PME and AER interrupts registered to MSI without this change, >> cat /proc/interrupts | grep -i pci >> 36: 21 0 0 0 0 0 GICv2 104 Level PCIE >> 37: 35 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI >> 76: 0 0 0 0 0 0 Tegra PCIe MSI 0 Edge PCIe PME, aerdrv, PCIe BW notif >> >> PME and AER interrupts registered to legacy IRQ with this change, >> cat /proc/interrupts | grep -i pci >> 36: 33 0 0 0 0 0 GICv2 104 Level PCIE, PCIe PME, aerdrv, PCIe BW notif >> 37: 52 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI >> >> Signed-off-by: Manikanta Maddireddy >> --- >> V6: Replaced pcie_pme_disable_msi() with no_msi quirk >> >> V5: No change >> >> V4: No change >> >> V3: Corrected typo in commit log >> >> V2: No change >> >> drivers/pci/quirks.c | 39 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >> index a59ad09ce911..20dcad421991 100644 >> --- a/drivers/pci/quirks.c >> +++ b/drivers/pci/quirks.c >> @@ -2576,6 +2576,45 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, >> PCI_DEVICE_ID_NVIDIA_NVENET_15, >> nvenet_msi_disable); >> >> +/* >> + * Tegra PCIe generates PME and AER events over legacy interrupt line. >> + * So disable msi for Tegra PCIe root ports. > s/msi/MSI/ > > What's going on here? Vidya posted a very similar patch [1] (although This series is focused on Tegra20, Tegra30, Tegra124, Tegra210 and Tegra186, whereas Vidya's series is focused only on Tegra194. So I didn't include Tegra194 device IDs. > his included nice spec citations, which you omitted), but his added > quirks for 0x1ad0, 0x1ad1, and 0x1ad2. You didn't include any of > those here. > > Maybe Lorenzo will sort this all out, but it would make things easier > if you and Vidya got together and integrated your patches yourselves > so Lorenzo didn't have to worry about it. > > [1] https://lore.kernel.org/lkml/20190612095339.20118-3-vidyas@nvidia.com I talked with Vidya, he will take this changes in his series if he needs to publish another version, or else he will publish a new patch to add quirk for legacy Tegra SOCs. Lorenzo, If this series is ready for integration, please drop this patch. Manikanta > >> + */ >> +static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) >> +{ >> + dev->no_msi = 1; >> +} >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> +DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, >> + PCI_CLASS_BRIDGE_PCI, 8, >> + pci_quirk_nvidia_tegra_disable_rp_msi); >> + >> /* >> * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing >> * config register. This register controls the routing of legacy >> -- >> 2.17.1 >>