From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7E491C8FBE; Fri, 6 Sep 2024 09:56:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725616591; cv=none; b=HFZEph6XlSVQ+ebxudBAj2N0Y9i+vRjtGmAmlRsy+Nh2J+8720JFTg9iUK6AqG3qBw3VMBLYeh9aUZTU2MDIswfO3Z8mW9dZCCiuACJs7FO0AjQD4sEYM8WY0GXJjcx9h/vMxduUv42L3fBkGrzKCm9z1zpXfqNcl70HWQQt52g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725616591; c=relaxed/simple; bh=fRb6iA5CazlU8a/FnHVGObboncCPam7WcbstuDBqWJs=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=bYhzDjEXoGfhq+1k92zvBCbxBx/YHBnkjdesTBz4Iy0Y1ZbTpDEyK+zEMqEnp0PFfR7wyeHNfABLOS5JtZRvfEQ4ialwm6tieONFTX4b+gaWOaX+bufRdi1VdoD6ThiiY4rzTMr2dgXXWKBKwXuquXlzASdusRhVk3DeYXQ7Xf4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PWOSnZWs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PWOSnZWs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2964DC4CEC4; Fri, 6 Sep 2024 09:56:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725616591; bh=fRb6iA5CazlU8a/FnHVGObboncCPam7WcbstuDBqWJs=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=PWOSnZWsgVAJrRh7NZN4vjWEkfLd/GxXf+4qmIcqLIEok22/5V+RZTVqr5mE2pH5h E63Bn4R2efuNX2Lkd4Z1i2p0OE8F0hZl1RmRbeR9Zmw/wxoaiSZ9ZWwMekrCOLRoH2 zYtVMuZzX+wLuKZKr+lQP+LsQtjFZemooTRzF5L2EIqnjGkoDYExd8A0oh3uT6WEPJ GNtcqwzlVJOctp06RkG5UHR9mWQGD4wB3jbmzx1ApiaB2nUbwK4THIaYoBMlZ5WysU Q+aLJqUqujGV1fALaAPUaM4oM/fTBmUL2ojGBubae9XlMF2UQiPCJ0pfh8H50uW6Q7 c8gav+BntVuXw== Message-ID: Date: Fri, 6 Sep 2024 11:56:23 +0200 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] PCI: xilinx-cpm: Add support for Versal CPM5 Root Port controller-1 To: Thippeswamy Havalige , manivannan.sadhasivam@linaro.org, robh@kernel.org, linux-pci@vger.kernel.org, bhelgaas@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: bharat.kumar.gogada@amd.com, michal.simek@amd.com, lpieralisi@kernel.org, kw@linux.com References: <20240906093148.830452-1-thippesw@amd.com> <20240906093148.830452-3-thippesw@amd.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 06/09/2024 11:31, Thippeswamy Havalige wrote: > In the CPM5, controller-1 has platform-specific error interrupt bits > located at different offsets compared to controller-0. > > Signed-off-by: Thippeswamy Havalige > --- > drivers/pci/controller/pcie-xilinx-cpm.c | 39 +++++++++++++++++++----- > 1 file changed, 32 insertions(+), 7 deletions(-) > > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c b/drivers/pci/controller/pcie-xilinx-cpm.c > index a0f5e1d67b04..d672f620bc4c 100644 > --- a/drivers/pci/controller/pcie-xilinx-cpm.c > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c > @@ -30,10 +30,13 @@ > #define XILINX_CPM_PCIE_REG_IDRN_MASK 0x00000E3C > #define XILINX_CPM_PCIE_MISC_IR_STATUS 0x00000340 > #define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348 > -#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1) > +#define XILINX_CPM_PCIE0_MISC_IR_LOCAL BIT(1) > +#define XILINX_CPM_PCIE1_MISC_IR_LOCAL BIT(2) > > -#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0 > -#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8 > +#define XILINX_CPM_PCIE0_IR_STATUS 0x000002A0 > +#define XILINX_CPM_PCIE1_IR_STATUS 0x000002B4 > +#define XILINX_CPM_PCIE0_IR_ENABLE 0x000002A8 > +#define XILINX_CPM_PCIE1_IR_ENABLE 0x000002BC > #define XILINX_CPM_PCIE_IR_LOCAL BIT(0) > > #define IMR(x) BIT(XILINX_PCIE_INTR_ ##x) > @@ -280,10 +283,17 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc) > pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR); > > if (port->variant->version == CPM5) { > - val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS); > + val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE0_IR_STATUS); > if (val) > writel_relaxed(val, port->cpm_base + > - XILINX_CPM_PCIE_IR_STATUS); > + XILINX_CPM_PCIE0_IR_STATUS); > + } > + There are no blank lines allowed between arms of conditional statements. Please follow coding style. This case is explained there. Best regards, Krzysztof