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From: "Bowman, Terry" <terry.bowman@amd.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v18 02/13] acpi/apei/ghes: Use raw_spinlock_t for CXL CPER work locks
Date: Mon, 20 Jul 2026 10:02:05 -0500	[thread overview]
Message-ID: <e4e1bb5b-2cc3-452c-9499-d74aa41965e6@amd.com> (raw)
In-Reply-To: <20260717224919.9F80E1F000E9@smtp.kernel.org>


The LOW issue is valid and the extra cancel_work_sync() needs to be 
removed. I propose we fix if a series respin is necessary or otherwise 
fix in future. 

The preexisting HIGH issues are GHES area and to be fixed by owners.

Terry 

On 7/17/2026 5:49 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
> 
> New issues:
> - [Low] The patch adds internal cancellation to both unregister functions but misses removing the redundant `cancel_work_sync()` for the protocol error work in `cxl_ras_exit()`.
> 
> Pre-existing issues:
> - [High] Fixed-size memcpy in cxl_cper_post_event causes an out-of-bounds read if the provided GHES CPER payload is smaller than sizeof(*rec).
> - [High] Missing bounds check on untrusted dvsec_len in cxl_cper_setup_prot_err_work_data leads to an out-of-bounds read.
> --
> 
> --- Patch [2]: [PATCH v18 02/13] acpi/apei/ghes: Use raw_spinlock_t for CXL CPER work locks ---
> commit 70fa064ce36bd35723148aab9a91c80d0fbef760
> Author: Terry Bowman <terry.bowman@amd.com>
> 
> acpi/apei/ghes: Use raw_spinlock_t for CXL CPER work locks
> 
> This commit converts cxl_cper_work_lock and cxl_cper_prot_err_work_lock from
> spinlock_t to raw_spinlock_t to prevent a deadlock between IRQ and process
> contexts. It also restructures registration functions to warn on double
> registration and clear work pointers before cancelling them. Redundant
> cancel_work_sync() calls are removed since quiescing is handled internally.
> 
>> diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
>> index 3236a3ce79d6b..ca7a138c1ff2e 100644
>> --- a/drivers/acpi/apei/ghes.c
>> +++ b/drivers/acpi/apei/ghes.c
> [ ... ]
>> @@ -761,7 +761,7 @@ static void cxl_cper_post_prot_err(struct cxl_cper_sec_prot_err *prot_err,
>>  	if (cxl_cper_sec_prot_err_valid(prot_err))
>>  		return;
>>  
>> -	guard(spinlock_irqsave)(&cxl_cper_prot_err_work_lock);
>> +	guard(raw_spinlock_irqsave)(&cxl_cper_prot_err_work_lock);
>>  
>>  	if (!cxl_cper_prot_err_work)
>>  		return;
> 
> [Severity: High]
> This is a pre-existing issue, but does cxl_cper_setup_prot_err_work_data()
> lack bounds checking on the untrusted dvsec_len?
> 
> If firmware provides a CXL protocol error record with a maliciously large
> dvsec_len, could this lead to an out-of-bounds read when calculating
> cap_start?
> 
> drivers/acpi/apei/ghes_helpers.c:cxl_cper_setup_prot_err_work_data() {
>     ...
>     dvsec_start = (u8 *)(prot_err + 1);
>     cap_start = dvsec_start + prot_err->dvsec_len;
> 
>     memcpy(&wd->ras_cap, cap_start, sizeof(wd->ras_cap));
>     ...
> }
> 
> [ ... ]
>> @@ -831,7 +839,7 @@ static void cxl_cper_post_event(enum cxl_event_type event_type,
>>  		return;
>>  	}
>>  
>> -	guard(spinlock_irqsave)(&cxl_cper_work_lock);
>> +	guard(raw_spinlock_irqsave)(&cxl_cper_work_lock);
>>  
>>  	if (!cxl_cper_work)
>>  		return;
> 
> [Severity: High]
> This is a pre-existing issue, but does cxl_cper_post_event() have an
> out-of-bounds read if the provided GHES CPER payload is smaller than
> sizeof(*rec)?
> 
> If firmware provides a CXL event record where gdata->error_data_length is
> smaller than sizeof(struct cxl_cper_event_rec), this fixed-size memcpy
> could exceed the bounds of the error status block:
> 
> drivers/acpi/apei/ghes.c:cxl_cper_post_event() {
>     ...
>     wd.event_type = event_type;
>     memcpy(&wd.rec, rec, sizeof(wd.rec));
>     ...
> }
> 
> [ ... ]
>> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
>> index 267c679b0b3c2..7c6faee7f85ed 100644
>> --- a/drivers/cxl/pci.c
>> +++ b/drivers/cxl/pci.c
>> @@ -1083,7 +1083,6 @@ static int __init cxl_pci_driver_init(void)
>>  static void __exit cxl_pci_driver_exit(void)
>>  {
>>  	cxl_cper_unregister_work(&cxl_cper_work);
>> -	cancel_work_sync(&cxl_cper_work);
>>  	pci_unregister_driver(&cxl_pci_driver);
>>  }
> 
> [Severity: Low]
> Is there a missed redundant cancel_work_sync() call in cxl_ras_exit()
> that should also be removed?
> 
> Since internal cancellation was added to the unregister functions,
> cxl_ras_exit() now has redundant synchronization:
> 
> drivers/cxl/core/ras.c:cxl_ras_exit() {
>     ...
>     cxl_cper_unregister_prot_err_work(&cxl_cper_prot_err_work);
>     cancel_work_sync(&cxl_cper_prot_err_work);
>     ...
> }
> 


  reply	other threads:[~2026-07-20 15:02 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-17 22:26 [PATCH v18 00/13] Enable CXL PCIe Port Protocol Error handling and logging Terry Bowman
2026-07-17 22:26 ` [PATCH v18 01/13] cxl/ras: Fix cxl_rch_get_aer_severity() wrong severity register Terry Bowman
2026-07-17 22:43   ` sashiko-bot
2026-07-20 20:09   ` Dave Jiang
2026-07-20 20:36     ` Bowman, Terry
2026-07-20 21:26   ` Jonathan Cameron
2026-07-17 22:26 ` [PATCH v18 02/13] acpi/apei/ghes: Use raw_spinlock_t for CXL CPER work locks Terry Bowman
2026-07-17 22:49   ` sashiko-bot
2026-07-20 15:02     ` Bowman, Terry [this message]
2026-07-20 21:36       ` Jonathan Cameron
2026-07-20 20:12   ` Dave Jiang
2026-07-20 20:38     ` Bowman, Terry
2026-07-20 21:41   ` Jonathan Cameron
2026-07-17 22:26 ` [PATCH v18 03/13] cxl: Tighten CPER kfifo registration API and symbol visibility Terry Bowman
2026-07-17 22:37   ` sashiko-bot
2026-07-20 20:15   ` Dave Jiang
2026-07-20 21:59   ` Jonathan Cameron
2026-07-17 22:26 ` [PATCH v18 04/13] cxl: Rename find_cxl_port() to find_cxl_port_by_dport() Terry Bowman
2026-07-17 22:34   ` sashiko-bot
2026-07-20 20:25   ` Dave Jiang
2026-07-20 22:02   ` Jonathan Cameron
2026-07-17 22:26 ` [PATCH v18 05/13] PCI/AER: Introduce AER-CXL protocol error kfifo Terry Bowman
2026-07-17 22:35   ` sashiko-bot
2026-07-20 20:29   ` Dave Jiang
2026-07-20 22:41   ` Jonathan Cameron
2026-07-17 22:26 ` [PATCH v18 06/13] PCI: Establish common CXL Port protocol error flow Terry Bowman
2026-07-17 22:43   ` sashiko-bot
2026-07-20 20:44   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 07/13] PCI/CXL: Add RCH support to CXL handlers Terry Bowman
2026-07-17 22:43   ` sashiko-bot
2026-07-20 15:06     ` Bowman, Terry
2026-07-20 21:47   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 08/13] cxl/pci: Thread port and dport through RAS handling helpers Terry Bowman
2026-07-17 22:40   ` sashiko-bot
2026-07-20 22:15   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 09/13] cxl: Update CXL Endpoint AER handler Terry Bowman
2026-07-17 22:53   ` sashiko-bot
2026-07-20 15:09     ` Bowman, Terry
2026-07-20 22:25   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 10/13] cxl: Add port and dport identifiers to CXL AER trace events Terry Bowman
2026-07-17 22:53   ` sashiko-bot
2026-07-20 15:14     ` Bowman, Terry
2026-07-20 22:44   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 11/13] PCI: Cache PCI DSN into pci_dev->dsn during probe Terry Bowman
2026-07-17 22:44   ` sashiko-bot
2026-07-18  7:02   ` Lukas Wunner
2026-07-20 15:48     ` Bowman, Terry
2026-07-17 22:27 ` [PATCH v18 12/13] PCI/CXL: Mask/Unmask CXL protocol errors Terry Bowman
2026-07-17 22:58   ` sashiko-bot
2026-07-20 22:52   ` Dave Jiang
2026-07-17 22:27 ` [PATCH v18 13/13] Documentation: cxl: Document CXL protocol error handling Terry Bowman
2026-07-17 22:43   ` sashiko-bot

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