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Fri, 30 Jan 2026 05:55:17 -0800 (PST) Message-ID: Date: Fri, 30 Jan 2026 15:55:16 +0200 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 10/15] PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility To: John Madieu , claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org Cc: robh@kernel.org, bhelgaas@google.com, conor+dt@kernel.org, magnus.damm@gmail.com, biju.das.jz@bp.renesas.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, john.madieu@gmail.com References: <20260129214130.16067-1-john.madieu.xa@bp.renesas.com> <20260129214130.16067-11-john.madieu.xa@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20260129214130.16067-11-john.madieu.xa@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, John, On 1/29/26 23:41, John Madieu wrote: > Program the class code register explicitly during PCIe configuration > initialization. RZ/G3E requires this register to be set, while RZ/G3S > has these values as hardware defaults. > > This configuration is harmless for RZ/G3S where these match the hardware > defaults, and necessary for RZ/G3E to properly identify the device as a > PCI bridge. > > Signed-off-by: John Madieu > --- > > Changes: > > v4: No changes > v3: No changes > v2: No changes > > drivers/pci/controller/pcie-rzg3s-host.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c > index 15ccd9095a3e..76f6d940ba45 100644 > --- a/drivers/pci/controller/pcie-rzg3s-host.c > +++ b/drivers/pci/controller/pcie-rzg3s-host.c > @@ -1054,6 +1054,7 @@ static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) > static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) > { > struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); > + u32 mask = GENMASK(31, 8); > struct resource_entry *ft; > struct resource *bus; > u8 subordinate_bus; > @@ -1077,6 +1078,13 @@ static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) > writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); > writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); > > + /* > + * Explicitly program class code. RZ/G3E requires this configuration. > + * Harmless for RZ/G3S where this matches the hardware default. > + */ > + rzg3s_pcie_update_bits(host->pcie, PCI_CLASS_REVISION, mask, > + FIELD_PREP(mask, PCI_CLASS_BRIDGE_PCI_NORMAL)); According to kernel test robot report on v1 this throws a compilation warning: https://lore.kernel.org/all/202601152104.pV9uMS76-lkp@intel.com/ > + > /* Disable access control to the CFGU */ > writel_relaxed(0, host->axi + RZG3S_PCI_PERM); >