* [PATCH] PCI: cadence: Enable support for applying lane equalization presets
@ 2025-10-27 13:29 Siddharth Vadapalli
2025-10-28 5:16 ` kernel test robot
0 siblings, 1 reply; 6+ messages in thread
From: Siddharth Vadapalli @ 2025-10-27 13:29 UTC (permalink / raw)
To: lpieralisi, kwilczynski, mani, robh, bhelgaas, unicorn_wang,
kishon, 18255117159
Cc: linux-pci, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe Link Equalization procedure allows peers on a PCIe Link to
improve the signal quality by exchanging transmitter presets and
receiver preset hints in the form of Ordered Sets.
For link speeds of 8.0 GT/s and above, the transmitter presets and the
receiver preset hints are configurable parameters which can be tuned to
establish a stable link. This allows setting up a stable link that is
specific to the peers across a Link.
The device-tree property 'eq-presets-Ngts' (eq-presets-8gts,
eq-presets-16gts, ...) specifies the transmitter presets and receiver
preset hints to be applied to every lane of the link for every supported
link speed that is greater than or equal to 8.0 GT/s.
Hence, enable support for applying the 'optional' lane equalization
presets when operating in the Root-Port (Root-Complex / Host) mode.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on linux-next tagged 20251027.
It also applies cleanly on 6.18-rc1.
Patch has been tested on J784S4-EVM which has 2 instances of PCIe,
namely PCIe0 and PCIe1. The diff corresponding to the device-tree change
for applying Presets to PCIe0 is:
https://gist.github.com/Siddharth-Vadapalli-at-TI/892ff417df178fcdf502e70d41bf5b48
An NVMe SSD has been connected to the PCIe connector for PCIe0 and
functionality has been validated after applying the current patch.
Test Logs:
https://gist.github.com/Siddharth-Vadapalli-at-TI/481e3ae5d359907cd9c3d9797ea028cc
Regards,
Siddharth.
.../controller/cadence/pcie-cadence-host.c | 84 +++++++++++++++++++
drivers/pci/controller/cadence/pcie-cadence.h | 5 ++
2 files changed, 89 insertions(+)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
index fffd63d6665e..3fac89703c0c 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-host.c
+++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
@@ -168,6 +168,89 @@ static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
}
+static void cdns_pcie_setup_lane_equalization_presets(struct cdns_pcie_rc *rc)
+{
+ struct cdns_pcie *pcie = &rc->pcie;
+ struct device *dev = pcie->dev;
+ struct device_node *np = dev->of_node;
+ int max_link_speed, max_lanes, ret;
+ u32 lane_eq_ctrl_reg;
+ u16 cap;
+ u16 *presets_8gts;
+ u8 *presets_ngts;
+ u8 i, j;
+
+ ret = of_property_read_u32(np, "num-lanes", &max_lanes);
+ if (ret)
+ return;
+
+ /* Lane Equalization presets are optional, so error message is not necessary */
+ ret = of_pci_get_equalization_presets(dev, &rc->eq_presets, max_lanes);
+ if (ret)
+ return;
+
+ max_link_speed = of_pci_get_max_link_speed(np);
+ if (max_link_speed < 0) {
+ dev_err(dev, "%s: link-speed unknown, skipping preset setup\n", __func__);
+ return;
+ }
+
+ /*
+ * Setup presets for data rates including and upward of 8.0 GT/s until the
+ * maximum supported data rate.
+ */
+ switch (pcie_link_speed[max_link_speed]) {
+ case PCIE_SPEED_16_0GT:
+ presets_ngts = (u8 *)rc->eq_presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1];
+ if (presets_ngts[0] != PCI_EQ_RESV) {
+ cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_PL_16GT);
+ if (!cap)
+ break;
+ lane_eq_ctrl_reg = cap + PCI_PL_16GT_LE_CTRL;
+ /*
+ * For Link Speeds including and upward of 16.0 GT/s, the Lane Equalization
+ * Control register has the following layout per Lane:
+ * Bits 0-3: Downstream Port Transmitter Preset
+ * Bits 4-7: Upstream Port Transmitter Preset
+ *
+ * 'eq_presets_Ngts' is an array of u8 (byte).
+ * Therefore, we need to write to the Lane Equalization Control
+ * register in units of bytes per-Lane.
+ */
+ for (i = 0; i < max_lanes; i++)
+ cdns_pcie_rp_writeb(pcie, lane_eq_ctrl_reg + i, presets_ngts[i]);
+
+ dev_info(dev, "Link Equalization presets applied for 16.0 GT/s\n");
+ }
+ case PCIE_SPEED_8_0GT:
+ presets_8gts = (u16 *)rc->eq_presets.eq_presets_8gts;
+ if ((presets_8gts[0] & PCI_EQ_RESV) != PCI_EQ_RESV) {
+ cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SECPCI);
+ if (!cap)
+ break;
+ lane_eq_ctrl_reg = cap + PCI_SECPCI_LE_CTRL;
+ /*
+ * For a Link Speed of 8.0 GT/s, the Lane Equalization Control register has
+ * the following layout per Lane:
+ * Bits 0-3: Downstream Port Transmitter Preset
+ * Bits 4-6: Downstream Port Receiver Preset Hint
+ * Bit 7: Reserved
+ * Bits 8-11: Upstream Port Transmitter Preset
+ * Bits 12-14: Upstream Port Receiver Preset Hint
+ * Bit 15: Reserved
+ *
+ * 'eq_presets_8gts' is an array of u16 (word).
+ * Therefore, we need to write to the Lane Equalization Control
+ * register in units of words per-Lane.
+ */
+ for (i = 0, j = 0; i < max_lanes; i++, j += 2)
+ cdns_pcie_rp_writew(pcie, lane_eq_ctrl_reg + j, presets_8gts[i]);
+
+ dev_info(dev, "Link Equalization presets applied for 8.0 GT/s\n");
+ }
+ }
+}
+
static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
{
struct cdns_pcie *pcie = &rc->pcie;
@@ -600,6 +683,7 @@ int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc)
cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
cdns_pcie_host_enable_ptm_response(pcie);
+ cdns_pcie_setup_lane_equalization_presets(rc);
ret = cdns_pcie_start_link(pcie);
if (ret) {
diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
index e2a853d2c0ab..39d03b309978 100644
--- a/drivers/pci/controller/cadence/pcie-cadence.h
+++ b/drivers/pci/controller/cadence/pcie-cadence.h
@@ -11,6 +11,8 @@
#include <linux/pci-epf.h>
#include <linux/phy/phy.h>
+#include "../../pci.h"
+
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
#define LINK_WAIT_USLEEP_MIN 90000
@@ -288,6 +290,8 @@ struct cdns_pcie {
* available
* @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2
* @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
+ * @eq_presets: Lane Equalization presets for Link Speed including and upward
+ * of 8.0 GT/s
*/
struct cdns_pcie_rc {
struct cdns_pcie pcie;
@@ -298,6 +302,7 @@ struct cdns_pcie_rc {
bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
unsigned int quirk_retrain_flag:1;
unsigned int quirk_detect_quiet_flag:1;
+ struct pci_eq_presets eq_presets;
};
/**
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
2025-10-27 13:29 [PATCH] PCI: cadence: Enable support for applying lane equalization presets Siddharth Vadapalli
@ 2025-10-28 5:16 ` kernel test robot
2025-10-28 5:26 ` Siddharth Vadapalli
0 siblings, 1 reply; 6+ messages in thread
From: kernel test robot @ 2025-10-28 5:16 UTC (permalink / raw)
To: Siddharth Vadapalli, lpieralisi, kwilczynski, mani, robh,
bhelgaas, unicorn_wang, kishon, 18255117159
Cc: oe-kbuild-all, linux-pci, linux-kernel, linux-arm-kernel, srk,
s-vadapalli
Hi Siddharth,
kernel test robot noticed the following build warnings:
[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus linus/master v6.18-rc3 next-20251027]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vadapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/20251027-213657
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-vadapalli%40ti.com
patch subject: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
config: x86_64-buildonly-randconfig-002-20251028 (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI-lkp@intel.com/
All warnings (new ones prefixed by >>):
drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'cdns_pcie_setup_lane_equalization_presets':
>> drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
205 | if (presets_ngts[0] != PCI_EQ_RESV) {
| ^
drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: here
225 | case PCIE_SPEED_8_0GT:
| ^~~~
vim +205 drivers/pci/controller/cadence/pcie-cadence-host.c
170
171 static void cdns_pcie_setup_lane_equalization_presets(struct cdns_pcie_rc *rc)
172 {
173 struct cdns_pcie *pcie = &rc->pcie;
174 struct device *dev = pcie->dev;
175 struct device_node *np = dev->of_node;
176 int max_link_speed, max_lanes, ret;
177 u32 lane_eq_ctrl_reg;
178 u16 cap;
179 u16 *presets_8gts;
180 u8 *presets_ngts;
181 u8 i, j;
182
183 ret = of_property_read_u32(np, "num-lanes", &max_lanes);
184 if (ret)
185 return;
186
187 /* Lane Equalization presets are optional, so error message is not necessary */
188 ret = of_pci_get_equalization_presets(dev, &rc->eq_presets, max_lanes);
189 if (ret)
190 return;
191
192 max_link_speed = of_pci_get_max_link_speed(np);
193 if (max_link_speed < 0) {
194 dev_err(dev, "%s: link-speed unknown, skipping preset setup\n", __func__);
195 return;
196 }
197
198 /*
199 * Setup presets for data rates including and upward of 8.0 GT/s until the
200 * maximum supported data rate.
201 */
202 switch (pcie_link_speed[max_link_speed]) {
203 case PCIE_SPEED_16_0GT:
204 presets_ngts = (u8 *)rc->eq_presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1];
> 205 if (presets_ngts[0] != PCI_EQ_RESV) {
206 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_PL_16GT);
207 if (!cap)
208 break;
209 lane_eq_ctrl_reg = cap + PCI_PL_16GT_LE_CTRL;
210 /*
211 * For Link Speeds including and upward of 16.0 GT/s, the Lane Equalization
212 * Control register has the following layout per Lane:
213 * Bits 0-3: Downstream Port Transmitter Preset
214 * Bits 4-7: Upstream Port Transmitter Preset
215 *
216 * 'eq_presets_Ngts' is an array of u8 (byte).
217 * Therefore, we need to write to the Lane Equalization Control
218 * register in units of bytes per-Lane.
219 */
220 for (i = 0; i < max_lanes; i++)
221 cdns_pcie_rp_writeb(pcie, lane_eq_ctrl_reg + i, presets_ngts[i]);
222
223 dev_info(dev, "Link Equalization presets applied for 16.0 GT/s\n");
224 }
225 case PCIE_SPEED_8_0GT:
226 presets_8gts = (u16 *)rc->eq_presets.eq_presets_8gts;
227 if ((presets_8gts[0] & PCI_EQ_RESV) != PCI_EQ_RESV) {
228 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SECPCI);
229 if (!cap)
230 break;
231 lane_eq_ctrl_reg = cap + PCI_SECPCI_LE_CTRL;
232 /*
233 * For a Link Speed of 8.0 GT/s, the Lane Equalization Control register has
234 * the following layout per Lane:
235 * Bits 0-3: Downstream Port Transmitter Preset
236 * Bits 4-6: Downstream Port Receiver Preset Hint
237 * Bit 7: Reserved
238 * Bits 8-11: Upstream Port Transmitter Preset
239 * Bits 12-14: Upstream Port Receiver Preset Hint
240 * Bit 15: Reserved
241 *
242 * 'eq_presets_8gts' is an array of u16 (word).
243 * Therefore, we need to write to the Lane Equalization Control
244 * register in units of words per-Lane.
245 */
246 for (i = 0, j = 0; i < max_lanes; i++, j += 2)
247 cdns_pcie_rp_writew(pcie, lane_eq_ctrl_reg + j, presets_8gts[i]);
248
249 dev_info(dev, "Link Equalization presets applied for 8.0 GT/s\n");
250 }
251 }
252 }
253
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
2025-10-28 5:16 ` kernel test robot
@ 2025-10-28 5:26 ` Siddharth Vadapalli
2025-10-28 11:47 ` Bjorn Helgaas
0 siblings, 1 reply; 6+ messages in thread
From: Siddharth Vadapalli @ 2025-10-28 5:26 UTC (permalink / raw)
To: kernel test robot
Cc: lpieralisi, kwilczynski, mani, robh, bhelgaas, unicorn_wang,
kishon, 18255117159, oe-kbuild-all, linux-pci, linux-kernel,
linux-arm-kernel, srk, s-vadapalli
On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote:
> Hi Siddharth,
>
> kernel test robot noticed the following build warnings:
>
> [auto build test WARNING on pci/next]
> [also build test WARNING on pci/for-linus linus/master v6.18-rc3 next-20251027]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch#_base_tree_information]
>
> url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vadapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/20251027-213657
> base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
> patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-vadapalli%40ti.com
> patch subject: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
> config: x86_64-buildonly-randconfig-002-20251028 (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config)
> compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
> reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce)
>
> If you fix the issue in a separate patch/commit (i.e. not just a new version of
> the same patch/commit), kindly add following tags
> > Reported-by: kernel test robot <lkp@intel.com>
> > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI-lkp@intel.com/
>
> All warnings (new ones prefixed by >>):
>
> drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'cdns_pcie_setup_lane_equalization_presets':
> > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
> 205 | if (presets_ngts[0] != PCI_EQ_RESV) {
> | ^
> drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: here
> 225 | case PCIE_SPEED_8_0GT:
> | ^~~~
Fallthrough is intentional. The lane equalization presets are programmed
starting from the Max Supported Link speed and we fallthrough until we get
to 8.0 GT/s.
Regards,
Siddharth.
>
>
> vim +205 drivers/pci/controller/cadence/pcie-cadence-host.c
>
> 170
> 171 static void cdns_pcie_setup_lane_equalization_presets(struct cdns_pcie_rc *rc)
> 172 {
> 173 struct cdns_pcie *pcie = &rc->pcie;
> 174 struct device *dev = pcie->dev;
> 175 struct device_node *np = dev->of_node;
> 176 int max_link_speed, max_lanes, ret;
> 177 u32 lane_eq_ctrl_reg;
> 178 u16 cap;
> 179 u16 *presets_8gts;
> 180 u8 *presets_ngts;
> 181 u8 i, j;
> 182
> 183 ret = of_property_read_u32(np, "num-lanes", &max_lanes);
> 184 if (ret)
> 185 return;
> 186
> 187 /* Lane Equalization presets are optional, so error message is not necessary */
> 188 ret = of_pci_get_equalization_presets(dev, &rc->eq_presets, max_lanes);
> 189 if (ret)
> 190 return;
> 191
> 192 max_link_speed = of_pci_get_max_link_speed(np);
> 193 if (max_link_speed < 0) {
> 194 dev_err(dev, "%s: link-speed unknown, skipping preset setup\n", __func__);
> 195 return;
> 196 }
> 197
> 198 /*
> 199 * Setup presets for data rates including and upward of 8.0 GT/s until the
> 200 * maximum supported data rate.
> 201 */
> 202 switch (pcie_link_speed[max_link_speed]) {
> 203 case PCIE_SPEED_16_0GT:
> 204 presets_ngts = (u8 *)rc->eq_presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1];
> > 205 if (presets_ngts[0] != PCI_EQ_RESV) {
> 206 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_PL_16GT);
> 207 if (!cap)
> 208 break;
> 209 lane_eq_ctrl_reg = cap + PCI_PL_16GT_LE_CTRL;
> 210 /*
> 211 * For Link Speeds including and upward of 16.0 GT/s, the Lane Equalization
> 212 * Control register has the following layout per Lane:
> 213 * Bits 0-3: Downstream Port Transmitter Preset
> 214 * Bits 4-7: Upstream Port Transmitter Preset
> 215 *
> 216 * 'eq_presets_Ngts' is an array of u8 (byte).
> 217 * Therefore, we need to write to the Lane Equalization Control
> 218 * register in units of bytes per-Lane.
> 219 */
> 220 for (i = 0; i < max_lanes; i++)
> 221 cdns_pcie_rp_writeb(pcie, lane_eq_ctrl_reg + i, presets_ngts[i]);
> 222
> 223 dev_info(dev, "Link Equalization presets applied for 16.0 GT/s\n");
> 224 }
> 225 case PCIE_SPEED_8_0GT:
> 226 presets_8gts = (u16 *)rc->eq_presets.eq_presets_8gts;
> 227 if ((presets_8gts[0] & PCI_EQ_RESV) != PCI_EQ_RESV) {
> 228 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SECPCI);
> 229 if (!cap)
> 230 break;
> 231 lane_eq_ctrl_reg = cap + PCI_SECPCI_LE_CTRL;
> 232 /*
> 233 * For a Link Speed of 8.0 GT/s, the Lane Equalization Control register has
> 234 * the following layout per Lane:
> 235 * Bits 0-3: Downstream Port Transmitter Preset
> 236 * Bits 4-6: Downstream Port Receiver Preset Hint
> 237 * Bit 7: Reserved
> 238 * Bits 8-11: Upstream Port Transmitter Preset
> 239 * Bits 12-14: Upstream Port Receiver Preset Hint
> 240 * Bit 15: Reserved
> 241 *
> 242 * 'eq_presets_8gts' is an array of u16 (word).
> 243 * Therefore, we need to write to the Lane Equalization Control
> 244 * register in units of words per-Lane.
> 245 */
> 246 for (i = 0, j = 0; i < max_lanes; i++, j += 2)
> 247 cdns_pcie_rp_writew(pcie, lane_eq_ctrl_reg + j, presets_8gts[i]);
> 248
> 249 dev_info(dev, "Link Equalization presets applied for 8.0 GT/s\n");
> 250 }
> 251 }
> 252 }
> 253
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
2025-10-28 5:26 ` Siddharth Vadapalli
@ 2025-10-28 11:47 ` Bjorn Helgaas
2025-10-28 12:43 ` Siddharth Vadapalli
0 siblings, 1 reply; 6+ messages in thread
From: Bjorn Helgaas @ 2025-10-28 11:47 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: kernel test robot, lpieralisi, kwilczynski, mani, robh, bhelgaas,
unicorn_wang, kishon, 18255117159, oe-kbuild-all, linux-pci,
linux-kernel, linux-arm-kernel, srk
On Tue, Oct 28, 2025 at 10:56:33AM +0530, Siddharth Vadapalli wrote:
> On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote:
> > Hi Siddharth,
> >
> > kernel test robot noticed the following build warnings:
> >
> > [auto build test WARNING on pci/next]
> > [also build test WARNING on pci/for-linus linus/master v6.18-rc3 next-20251027]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch#_base_tree_information]
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vadapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/20251027-213657
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
> > patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-vadapalli%40ti.com
> > patch subject: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
> > config: x86_64-buildonly-randconfig-002-20251028 (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config)
> > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
> > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce)
> >
> > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > the same patch/commit), kindly add following tags
> > > Reported-by: kernel test robot <lkp@intel.com>
> > > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI-lkp@intel.com/
> >
> > All warnings (new ones prefixed by >>):
> >
> > drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'cdns_pcie_setup_lane_equalization_presets':
> > > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
> > 205 | if (presets_ngts[0] != PCI_EQ_RESV) {
> > | ^
> > drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: here
> > 225 | case PCIE_SPEED_8_0GT:
> > | ^~~~
>
> Fallthrough is intentional. The lane equalization presets are programmed
> starting from the Max Supported Link speed and we fallthrough until we get
> to 8.0 GT/s.
It's poorly documented, but use "fallthrough" here:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/deprecated.rst?id=v6.17#n200
> > vim +205 drivers/pci/controller/cadence/pcie-cadence-host.c
> >
> > 170
> > 171 static void cdns_pcie_setup_lane_equalization_presets(struct cdns_pcie_rc *rc)
> > 172 {
> > 173 struct cdns_pcie *pcie = &rc->pcie;
> > 174 struct device *dev = pcie->dev;
> > 175 struct device_node *np = dev->of_node;
> > 176 int max_link_speed, max_lanes, ret;
> > 177 u32 lane_eq_ctrl_reg;
> > 178 u16 cap;
> > 179 u16 *presets_8gts;
> > 180 u8 *presets_ngts;
> > 181 u8 i, j;
> > 182
> > 183 ret = of_property_read_u32(np, "num-lanes", &max_lanes);
> > 184 if (ret)
> > 185 return;
> > 186
> > 187 /* Lane Equalization presets are optional, so error message is not necessary */
> > 188 ret = of_pci_get_equalization_presets(dev, &rc->eq_presets, max_lanes);
> > 189 if (ret)
> > 190 return;
> > 191
> > 192 max_link_speed = of_pci_get_max_link_speed(np);
> > 193 if (max_link_speed < 0) {
> > 194 dev_err(dev, "%s: link-speed unknown, skipping preset setup\n", __func__);
> > 195 return;
> > 196 }
> > 197
> > 198 /*
> > 199 * Setup presets for data rates including and upward of 8.0 GT/s until the
> > 200 * maximum supported data rate.
> > 201 */
> > 202 switch (pcie_link_speed[max_link_speed]) {
> > 203 case PCIE_SPEED_16_0GT:
> > 204 presets_ngts = (u8 *)rc->eq_presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS - 1];
> > > 205 if (presets_ngts[0] != PCI_EQ_RESV) {
> > 206 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_PL_16GT);
> > 207 if (!cap)
> > 208 break;
> > 209 lane_eq_ctrl_reg = cap + PCI_PL_16GT_LE_CTRL;
> > 210 /*
> > 211 * For Link Speeds including and upward of 16.0 GT/s, the Lane Equalization
> > 212 * Control register has the following layout per Lane:
> > 213 * Bits 0-3: Downstream Port Transmitter Preset
> > 214 * Bits 4-7: Upstream Port Transmitter Preset
> > 215 *
> > 216 * 'eq_presets_Ngts' is an array of u8 (byte).
> > 217 * Therefore, we need to write to the Lane Equalization Control
> > 218 * register in units of bytes per-Lane.
> > 219 */
> > 220 for (i = 0; i < max_lanes; i++)
> > 221 cdns_pcie_rp_writeb(pcie, lane_eq_ctrl_reg + i, presets_ngts[i]);
> > 222
> > 223 dev_info(dev, "Link Equalization presets applied for 16.0 GT/s\n");
> > 224 }
> > 225 case PCIE_SPEED_8_0GT:
> > 226 presets_8gts = (u16 *)rc->eq_presets.eq_presets_8gts;
> > 227 if ((presets_8gts[0] & PCI_EQ_RESV) != PCI_EQ_RESV) {
> > 228 cap = cdns_pcie_find_ext_capability(pcie, PCI_EXT_CAP_ID_SECPCI);
> > 229 if (!cap)
> > 230 break;
> > 231 lane_eq_ctrl_reg = cap + PCI_SECPCI_LE_CTRL;
> > 232 /*
> > 233 * For a Link Speed of 8.0 GT/s, the Lane Equalization Control register has
> > 234 * the following layout per Lane:
> > 235 * Bits 0-3: Downstream Port Transmitter Preset
> > 236 * Bits 4-6: Downstream Port Receiver Preset Hint
> > 237 * Bit 7: Reserved
> > 238 * Bits 8-11: Upstream Port Transmitter Preset
> > 239 * Bits 12-14: Upstream Port Receiver Preset Hint
> > 240 * Bit 15: Reserved
> > 241 *
> > 242 * 'eq_presets_8gts' is an array of u16 (word).
> > 243 * Therefore, we need to write to the Lane Equalization Control
> > 244 * register in units of words per-Lane.
> > 245 */
> > 246 for (i = 0, j = 0; i < max_lanes; i++, j += 2)
> > 247 cdns_pcie_rp_writew(pcie, lane_eq_ctrl_reg + j, presets_8gts[i]);
> > 248
> > 249 dev_info(dev, "Link Equalization presets applied for 8.0 GT/s\n");
> > 250 }
> > 251 }
> > 252 }
> > 253
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
2025-10-28 11:47 ` Bjorn Helgaas
@ 2025-10-28 12:43 ` Siddharth Vadapalli
2025-10-29 8:38 ` Siddharth Vadapalli
0 siblings, 1 reply; 6+ messages in thread
From: Siddharth Vadapalli @ 2025-10-28 12:43 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kernel test robot, lpieralisi, kwilczynski, mani, robh, bhelgaas,
unicorn_wang, kishon, 18255117159, oe-kbuild-all, linux-pci,
linux-kernel, linux-arm-kernel, srk, s-vadapalli
On Tue, 2025-10-28 at 06:47 -0500, Bjorn Helgaas wrote:
Hello Bjorn,
> On Tue, Oct 28, 2025 at 10:56:33AM +0530, Siddharth Vadapalli wrote:
> > On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote:
> > > Hi Siddharth,
> > >
> > > kernel test robot noticed the following build warnings:
> > >
> > > [auto build test WARNING on pci/next]
> > > [also build test WARNING on pci/for-linus linus/master v6.18-rc3 next-20251027]
> > > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > > And when submitting patch, we suggest to use '--base' as documented in
> > > https://git-scm.com/docs/git-format-patch#_base_tree_information]
> > >
> > > url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vadapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/20251027-213657
> > > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
> > > patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-vadapalli%40ti.com
> > > patch subject: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
> > > config: x86_64-buildonly-randconfig-002-20251028 (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config)
> > > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
> > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce)
> > >
> > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > the same patch/commit), kindly add following tags
> > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI-lkp@intel.com/
> > >
> > > All warnings (new ones prefixed by >>):
> > >
> > > drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'cdns_pcie_setup_lane_equalization_presets':
> > > > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
> > > 205 | if (presets_ngts[0] != PCI_EQ_RESV) {
> > > | ^
> > > drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: here
> > > 225 | case PCIE_SPEED_8_0GT:
> > > | ^~~~
> >
> > Fallthrough is intentional. The lane equalization presets are programmed
> > starting from the Max Supported Link speed and we fallthrough until we get
> > to 8.0 GT/s.
>
> It's poorly documented, but use "fallthrough" here:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/deprecated.rst?id=v6.17#n200
Thank you for pointing me to the documentation. I will update the patch
accordingly and post the v2 patch.
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
2025-10-28 12:43 ` Siddharth Vadapalli
@ 2025-10-29 8:38 ` Siddharth Vadapalli
0 siblings, 0 replies; 6+ messages in thread
From: Siddharth Vadapalli @ 2025-10-29 8:38 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: kernel test robot, lpieralisi, kwilczynski, mani, robh, bhelgaas,
unicorn_wang, kishon, 18255117159, oe-kbuild-all, linux-pci,
linux-kernel, linux-arm-kernel, srk, s-vadapalli
On Tue, 2025-10-28 at 18:13 +0530, Siddharth Vadapalli wrote:
> On Tue, 2025-10-28 at 06:47 -0500, Bjorn Helgaas wrote:
>
> Hello Bjorn,
>
> > On Tue, Oct 28, 2025 at 10:56:33AM +0530, Siddharth Vadapalli wrote:
> > > On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote:
> > > > Hi Siddharth,
> > > >
> > > > kernel test robot noticed the following build warnings:
> > > >
> > > > [auto build test WARNING on pci/next]
> > > > [also build test WARNING on pci/for-linus linus/master v6.18-rc3 next-20251027]
> > > > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > > > And when submitting patch, we suggest to use '--base' as documented in
> > > > https://git-scm.com/docs/git-format-patch#_base_tree_information]
> > > >
> > > > url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vadapalli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/20251027-213657
> > > > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
> > > > patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-vadapalli%40ti.com
> > > > patch subject: [PATCH] PCI: cadence: Enable support for applying lane equalization presets
> > > > config: x86_64-buildonly-randconfig-002-20251028 (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config)
> > > > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
> > > > reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce)
> > > >
> > > > If you fix the issue in a separate patch/commit (i.e. not just a new version of
> > > > the same patch/commit), kindly add following tags
> > > > > Reported-by: kernel test robot <lkp@intel.com>
> > > > > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI-lkp@intel.com/
> > > >
> > > > All warnings (new ones prefixed by >>):
> > > >
> > > > drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'cdns_pcie_setup_lane_equalization_presets':
> > > > > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warning: this statement may fall through [-Wimplicit-fallthrough=]
> > > > 205 | if (presets_ngts[0] != PCI_EQ_RESV) {
> > > > | ^
> > > > drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: here
> > > > 225 | case PCIE_SPEED_8_0GT:
> > > > | ^~~~
> > >
> > > Fallthrough is intentional. The lane equalization presets are programmed
> > > starting from the Max Supported Link speed and we fallthrough until we get
> > > to 8.0 GT/s.
> >
> > It's poorly documented, but use "fallthrough" here:
> >
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/deprecated.rst?id=v6.17#n200
>
> Thank you for pointing me to the documentation. I will update the patch
> accordingly and post the v2 patch.
I have posted the v2 patch at:
https://lore.kernel.org/r/20251028134601.3688030-1-s-vadapalli@ti.com/
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-10-29 8:38 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-10-27 13:29 [PATCH] PCI: cadence: Enable support for applying lane equalization presets Siddharth Vadapalli
2025-10-28 5:16 ` kernel test robot
2025-10-28 5:26 ` Siddharth Vadapalli
2025-10-28 11:47 ` Bjorn Helgaas
2025-10-28 12:43 ` Siddharth Vadapalli
2025-10-29 8:38 ` Siddharth Vadapalli
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