From: okaya@codeaurora.org
To: poza@codeaurora.org
Cc: Bjorn Helgaas <helgaas@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Philippe Ombredanne <pombredanne@nexb.com>,
Thomas Gleixner <tglx@linutronix.de>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Kate Stewart <kstewart@linuxfoundation.org>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
Dongdong Liu <liudongdong3@huawei.com>,
Keith Busch <keith.busch@intel.com>, Wei Zhang <wzhang@fb.com>,
Timur Tabi <timur@codeaurora.org>,
linux-pci-owner@vger.kernel.org
Subject: Re: [PATCH NEXT 6/6] PCI/PORTDRV: Remove ERR_FATAL handling from pcie_portdrv_slot_reset()
Date: Fri, 08 Jun 2018 06:41:48 -0400 [thread overview]
Message-ID: <eaa6c04259f0b41d5281d24c7422f914@codeaurora.org> (raw)
In-Reply-To: <bbce31a6e59fdfa00e565e09dcae9eea@codeaurora.org>
On 2018-06-08 00:57, poza@codeaurora.org wrote:
> On 2018-06-08 03:04, Bjorn Helgaas wrote:
>> On Thu, Jun 07, 2018 at 07:18:03PM +0530, poza@codeaurora.org wrote:
>>> On 2018-06-07 11:30, Oza Pawandeep wrote:
>>> > We are handling ERR_FATAL by resetting the Link in software,skipping the
>>> > driver pci_error_handlers callbacks, removing the devices from the PCI
>>> > subsystem, and re-enumerating, as a result of that, no more calling
>>> > pcie_portdrv_slot_reset in ERR_FATAL case.
>>> >
>>> > Signed-off-by: Oza Pawandeep <poza@codeaurora.org>
>>> >
>>> > diff --git a/drivers/pci/pcie/portdrv_pci.c
>>> > b/drivers/pci/pcie/portdrv_pci.c
>>> > index 973f1b8..92f5d330 100644
>>> > --- a/drivers/pci/pcie/portdrv_pci.c
>>> > +++ b/drivers/pci/pcie/portdrv_pci.c
>>> > @@ -42,17 +42,6 @@ __setup("pcie_ports=", pcie_port_setup);
>>> >
>>> > /* global data */
>>> >
>>> > -static int pcie_portdrv_restore_config(struct pci_dev *dev)
>>> > -{
>>> > - int retval;
>>> > -
>>> > - retval = pci_enable_device(dev);
>>> > - if (retval)
>>> > - return retval;
>>> > - pci_set_master(dev);
>>> > - return 0;
>>> > -}
>>> > -
>>> > #ifdef CONFIG_PM
>>> > static int pcie_port_runtime_suspend(struct device *dev)
>>> > {
>>> > @@ -162,14 +151,6 @@ static pci_ers_result_t
>>> > pcie_portdrv_mmio_enabled(struct pci_dev *dev)
>>> >
>>> > static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
>>> > {
>>> > - /* If fatal, restore cfg space for possible link reset at upstream */
>>> > - if (dev->error_state == pci_channel_io_frozen) {
>>> > - dev->state_saved = true;
>>> > - pci_restore_state(dev);
>>> > - pcie_portdrv_restore_config(dev);
>>> > - pci_enable_pcie_error_reporting(dev);
>>> > - }
>>> > -
>>> > return PCI_ERS_RESULT_RECOVERED;
>>> > }
>>>
>>>
>>> Hi Bjorn,
>>>
>>> the above patch removes ERR_FATAL handling from
>>> pcie_portdrv_slot_reset()
>>> because now we are handling ERR_FATAL differently than before.
>>>
>>> I tried to dig into pcie_portdrv_slot_reset() handling for ERR_FATAL
>>> case
>>> where it
>>> restores the config space, enable device, set master and enable error
>>> reporting....
>>> and as far as I understand this is being done for upstream link
>>> (bridges
>>> etc..)
>>>
>>> why was it done at the first point (I checked the commit description,
>>> but
>>> could not really get it)
>>> and do we need to handle the same thing in ERR_FATAL now ?
>>
>> You mean 4bf3392e0bf5 ("PCI-Express AER implemetation: pcie_portdrv
>> error handler"), which added pcie_portdrv_slot_reset()? I agree, that
>> commit log has no useful information. I don't know any of the history
>> behind it.
>
>
> Yes Bjorn thats right.
> I am trying to understand it but no clue.
> since it is restoring the stuffs in ERR_FATAL case, why would PCIe
> bridge loose all the settings ? [config space, aer bits, master,
> device enable etc..)
> Max we do is link_reset in ERR_FATAL case, and Secondary bus reset
> should affect downstream components (not upstream)
Our first generation controller had this problem. There could be others
too.
next prev parent reply other threads:[~2018-06-08 10:41 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-07 6:00 [PATCH NEXT 1/6] PCI/AER: Take mask into account while clearing error bits Oza Pawandeep
2018-06-07 6:00 ` [PATCH NEXT 2/6] PCI/AER: Clear uncorrectable fatal error status bits Oza Pawandeep
2018-06-07 6:00 ` [PATCH NEXT 3/6] PCI/ERR: Cleanup ERR_FATAL of error broadcast Oza Pawandeep
2018-06-07 6:00 ` [PATCH NEXT 4/6] PCI/AER: Clear device status error bits during ERR_FATAL and ERR_NONFATAL Oza Pawandeep
2018-06-07 6:00 ` [PATCH NEXT 5/6] PCI/AER: Clear correctable status bits in device register Oza Pawandeep
2018-06-07 6:00 ` [PATCH NEXT 6/6] PCI/PORTDRV: Remove ERR_FATAL handling from pcie_portdrv_slot_reset() Oza Pawandeep
2018-06-07 13:48 ` poza
2018-06-07 21:34 ` Bjorn Helgaas
2018-06-08 4:47 ` poza
2018-06-08 22:43 ` Keith Busch
2018-06-08 4:57 ` poza
2018-06-08 10:41 ` okaya [this message]
2018-06-11 10:01 ` poza
2018-06-11 12:50 ` poza
2018-06-07 13:21 ` [PATCH NEXT 1/6] PCI/AER: Take mask into account while clearing error bits Bjorn Helgaas
2018-06-07 13:44 ` poza
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