From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D027C43381 for ; Mon, 1 Apr 2019 05:43:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3F6DD20828 for ; Mon, 1 Apr 2019 05:43:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="EyuHmIXC" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727214AbfDAFnp (ORCPT ); Mon, 1 Apr 2019 01:43:45 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:9444 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725860AbfDAFnp (ORCPT ); Mon, 1 Apr 2019 01:43:45 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 31 Mar 2019 22:43:41 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 31 Mar 2019 22:43:43 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 31 Mar 2019 22:43:43 -0700 Received: from [10.24.47.153] (172.20.13.39) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Apr 2019 05:43:39 +0000 Subject: Re: [PATCH V2] PCI: tegra: Use the DMA-API to get the MSI address To: , CC: vidya sagar , , , , , , , , , NManikanta References: <1553004121-24606-1-git-send-email-vidyas@nvidia.com> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Mon, 1 Apr 2019 11:13:36 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL101.nvidia.com (172.20.187.10) Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1554097421; bh=x5o+McQVbvfpJWl2gClmRRIdzd1rfbnzE9l0zNSDb/0=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=EyuHmIXCVixZtsdO4ilIX5HDkm8zzz0tiEY2Y3/Zjs5Q8KCij6uE0Xlmpacd+43Pk yuRpTIppIAWQr59Shi+GW+lTYvBkNatxhTcoP89n1cyUFyc1CLkNL760XZFkKQBkoY ZMancyxw0GNoBg44zef0j7F88HMwloFZoekinpl8NeHdJg+ipaeTLU5ExneBwO4Vq+ Z6QdX0zro6h8R12ZcX2XJcrmc3XFZYyevlr+G+xYF+wM7F/+K1Jdz4gqHLmiDNPu67 NGmhvZxneh3lBSUuEy1PMD6r1nKgY5eZuOTWAHDu5dURHBS3yQT9FGY/zqqH0ypmIM y36jq8rztNyQw== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Bjorn / Lorenzo, Can you please review this patch? Thanks, Vidya Sagar On 3/27/2019 4:29 PM, vidya sagar wrote: > Hi Bjorn/Lorenzo, > Can you please review this patch? > Thierry has reviewed it and I already took care=C2=A0of=C2=A0his comments= . >=20 > Thanks, > Vidya Sagar >=20 > On Tue, Mar 19, 2019 at 7:33 PM Vidya Sagar > wrote: >=20 > Since the upstream MSI memory writes are generated by downstream devi= ces, > it is logically correct to have MSI target memory coming from the DMA= pool > reserved for PCIe than from the general memory pool reserved for CPU > access. This avoids PCIe DMA addresses coinciding with MSI target add= ress > thereby raising unwanted MSI interrupts. This patch also enforces to = limit > the MSI target address to 32-bits to make it work for PCIe endponits = that > support only 32-bit MSI target address and those endpoints that suppo= rt > 64-bit MSI target address anyway work with 32-bit MSI target address. >=20 > Signed-off-by: Vidya Sagar > > Reviewed-by: Thierry Reding > > Acked-by: Thierry Reding > > --- > v2: > * changed 'phys' type to 'dma_addr_t' from 'u64' > * added a comment on why DMA mask is set to 32-bit > * replaced 'dma' with 'DMA' >=20 > =C2=A0drivers/pci/controller/pci-tegra.c | 35 ++++++++++++++++++++++= ++++--------- > =C2=A01 file changed, 26 insertions(+), 9 deletions(-) >=20 > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/control= ler/pci-tegra.c > index f4f53d092e00..f8173a5e352d 100644 > --- a/drivers/pci/controller/pci-tegra.c > +++ b/drivers/pci/controller/pci-tegra.c > @@ -231,9 +231,9 @@ struct tegra_msi { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct msi_controller chip; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 DECLARE_BITMAP(used, INT_PCI_MSI_NR); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct irq_domain *domain; > -=C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned long pages; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct mutex lock; > -=C2=A0 =C2=A0 =C2=A0 =C2=A0u64 phys; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0void *virt; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0dma_addr_t phys; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 int irq; > =C2=A0}; >=20 > @@ -1536,7 +1536,7 @@ static int tegra_pcie_msi_setup(struct tegra_pc= ie *pcie) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 err =3D platform_get_irq_byname(pdev, "m= si"); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err < 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev,= "failed to get IRQ: %d\n", err); > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto err; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto free_irq= _domain; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 msi->irq =3D err; > @@ -1545,17 +1545,34 @@ static int tegra_pcie_msi_setup(struct tegra_= pcie *pcie) > tegra_msi_irq_chip.name , pcie); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (err < 0) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 dev_err(dev,= "failed to request IRQ: %d\n", err); > -=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto err; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto free_irq= _domain; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0} > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Though the PCIe controller can address= >32-bit address space, to > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * facilitate endpoints that support only= 32-bit MSI target address, > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * the mask is set to 32-bit to make sure= that MSI target address is > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 * always a 32-bit address > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 */ > +=C2=A0 =C2=A0 =C2=A0 =C2=A0err =3D dma_set_coherent_mask(dev, DMA_BI= T_MASK(32)); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0if (err < 0) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(dev, = "failed to set DMA coherent mask: %d\n", err); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto free_irq= ; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0} > + > +=C2=A0 =C2=A0 =C2=A0 =C2=A0msi->virt =3D dma_alloc_coherent(dev, PAG= E_SIZE, &msi->phys, GFP_KERNEL); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0if (!msi->virt) { > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0dev_err(dev, = "failed to allocate DMA memory for MSI\n"); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0err =3D -ENOM= EM; > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto free_irq= ; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 } >=20 > -=C2=A0 =C2=A0 =C2=A0 =C2=A0/* setup AFI/FPCI range */ > -=C2=A0 =C2=A0 =C2=A0 =C2=A0msi->pages =3D __get_free_pages(GFP_KERNE= L, 0); > -=C2=A0 =C2=A0 =C2=A0 =C2=A0msi->phys =3D virt_to_phys((void *)msi->p= ages); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 host->msi =3D &msi->chip; >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 return 0; >=20 > -err: > +free_irq: > +=C2=A0 =C2=A0 =C2=A0 =C2=A0free_irq(msi->irq, pcie); > +free_irq_domain: > =C2=A0 =C2=A0 =C2=A0 =C2=A0 irq_domain_remove(msi->domain); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 return err; > =C2=A0} > @@ -1592,7 +1609,7 @@ static void tegra_pcie_msi_teardown(struct tegr= a_pcie *pcie) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 struct tegra_msi *msi =3D &pcie->msi; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned int i, irq; >=20 > -=C2=A0 =C2=A0 =C2=A0 =C2=A0free_pages(msi->pages, 0); > +=C2=A0 =C2=A0 =C2=A0 =C2=A0dma_free_coherent(pcie->dev, PAGE_SIZE, m= si->virt, msi->phys); >=20 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (msi->irq > 0) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 free_irq(msi= ->irq, pcie); > --=20 > 2.7.4 >=20