From: valmiki <valmikibow@gmail.com>
To: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>,
Alex Williamson <alex.williamson@redhat.com>
Cc: iommu@lists.linux-foundation.org, kvm@vger.kernel.org,
linux-pci@vger.kernel.org, tianyu.lan@intel.com,
kevin.tian@intel.com, jacob.jun.pan@intel.com
Subject: Re: Support SVM without PASID
Date: Wed, 12 Jul 2017 21:57:21 +0530 [thread overview]
Message-ID: <ee41f5d9-e7fb-8f7c-4b85-87cdb951ec70@gmail.com> (raw)
In-Reply-To: <eb132dfa-6708-5898-c2ce-ce7ab08809b1@arm.com>
On 7/11/2017 4:26 PM, Jean-Philippe Brucker wrote:
> Hi Valmiki,
>
> On 09/07/17 04:15, valmiki wrote:
>>>> Hi,
>>>>
>>>> In SMMUv3 architecture document i see "PASIDs are optional,
>>>> configurable, and of a size determined by the minimum
>>>> of the endpoint".
>>>>
>>>> So if PASID's are optional and not supported by PCIe end point, how SVM
>>>> can be achieved ?
>>>
>>> It cannot be inferred from that statement that PASID support is not
>>> required for SVM. AIUI, SVM is a software feature enabled by numerous
>>> "optional" hardware features, including PASID. Features that are
>>> optional per the hardware specification may be required for specific
>>> software features. Thanks,
>>>
>> Thanks for the information Alex. Suppose if an End point doesn't support
>> PASID, is it still possible to achieve SVM ?
>> Are there any such features in SMMUv3 with which we can achieve it ?
>
> Not really, we don't plan to share the non-PASID context with a process.
>
> In theory you could achieve something resembling SVM by assigning the
> entire endpoint to userspace using VFIO, then use ATS+PRI capabilities
> with a bind ioctl. If your device can do SR-IOV, then you can bind one
> process per virtual function.
>
> Unless we end up seeing lots of endpoints that implement PRI but not
> PASID, I don't plan to add this to VFIO or SMMUv3.
>
> For a PCIe endpoint, the requirements for SVM are ATS, PRI and PASID
> enabled. In addition, the SMMU should support DVM (broadcast TLB
> maintenance) and must be compatible with the MMU (page sizes, output
> address size, ASID bits...)
>
Thanks Jean.
In SMMU document it was quoted as follows
"When STE.S1DSS==0b10, a transaction without a SubstreamID is accepted
and uses the CD of Substream 0. Under this configuration, transactions
that arrive with SubstreamID 0 are aborted and an event recorded."
Is this mode supported in your previous series of SMMUv3 patches ?
If it is supported is it achieved through VFIO ?
Regards,
Valmiki
next prev parent reply other threads:[~2017-07-12 16:27 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-08 17:03 Support SVM without PASID valmiki
2017-07-08 20:02 ` Alex Williamson
2017-07-09 3:15 ` valmiki
2017-07-09 9:29 ` Liu, Yi L
2017-07-10 0:14 ` Bob Liu
2017-07-10 19:31 ` Jerome Glisse
2017-07-12 16:23 ` valmiki
2017-07-11 10:56 ` Jean-Philippe Brucker
2017-07-12 16:27 ` valmiki [this message]
2017-07-12 16:48 ` Jean-Philippe Brucker
2017-07-22 2:05 ` valmiki
2017-08-01 8:26 ` Jean-Philippe Brucker
2017-08-01 17:38 ` valmiki
2017-08-01 18:40 ` Jean-Philippe Brucker
2017-08-05 5:14 ` valmiki
2017-08-07 10:31 ` Jean-Philippe Brucker
2017-08-07 12:18 ` Bob Liu
2017-08-07 12:52 ` Jean-Philippe Brucker
2017-08-08 0:51 ` Bob Liu
2017-08-09 15:01 ` Jean-Philippe Brucker
2017-08-11 6:41 ` Tian, Kevin
2017-08-11 9:25 ` Jean-Philippe Brucker
2017-08-11 9:36 ` Bob Liu
2017-08-12 12:10 ` valmiki
2017-08-14 7:49 ` Tian, Kevin
2017-08-28 13:10 ` Bharat Kumar Gogada
2017-08-29 1:32 ` Tian, Kevin
2017-08-04 1:49 ` Tian, Kevin
2017-08-04 9:42 ` Jean-Philippe Brucker
2017-08-11 6:29 ` Tian, Kevin
2017-08-11 16:25 ` Raj, Ashok
2017-08-14 8:00 ` Tian, Kevin
2017-08-14 9:07 ` Jean-Philippe Brucker
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