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Tue, 28 Oct 2025 07:43:39 -0500 Received: from [10.24.73.74] (uda0492258.dhcp.ti.com [10.24.73.74]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 59SChZUo2338171; Tue, 28 Oct 2025 07:43:35 -0500 Message-ID: Subject: Re: [PATCH] PCI: cadence: Enable support for applying lane equalization presets From: Siddharth Vadapalli To: Bjorn Helgaas CC: kernel test robot , , , , , , , , <18255117159@163.com>, , , , , , Date: Tue, 28 Oct 2025 18:13:46 +0530 In-Reply-To: <20251028114746.GA1505797@bhelgaas> References: <20251028114746.GA1505797@bhelgaas> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.1-1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD9:EE_|CH3PR10MB7987:EE_ X-MS-Office365-Filtering-Correlation-Id: 5d05864e-73a8-4606-6a17-08de161fa155 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|1800799024|36860700013|34070700014|32650700017|34020700016|34110700003|34140700187; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Oct 2025 12:43:43.8642 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5d05864e-73a8-4606-6a17-08de161fa155 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.23.194];Helo=[lewvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR10MB7987 On Tue, 2025-10-28 at 06:47 -0500, Bjorn Helgaas wrote: Hello Bjorn, > On Tue, Oct 28, 2025 at 10:56:33AM +0530, Siddharth Vadapalli wrote: > > On Tue, 2025-10-28 at 13:16 +0800, kernel test robot wrote: > > > Hi Siddharth, > > >=20 > > > kernel test robot noticed the following build warnings: > > >=20 > > > [auto build test WARNING on pci/next] > > > [also build test WARNING on pci/for-linus linus/master v6.18-rc3 next= -20251027] > > > [If your patch is applied to the wrong git tree, kindly drop us a not= e. > > > And when submitting patch, we suggest to use '--base' as documented i= n > > > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > >=20 > > > url: https://github.com/intel-lab-lkp/linux/commits/Siddharth-Vada= palli/PCI-cadence-Enable-support-for-applying-lane-equalization-presets/202= 51027-213657 > > > base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git n= ext > > > patch link: https://lore.kernel.org/r/20251027133013.2589119-1-s-v= adapalli%40ti.com > > > patch subject: [PATCH] PCI: cadence: Enable support for applying lane= equalization presets > > > config: x86_64-buildonly-randconfig-002-20251028 (https://download.01= .org/0day-ci/archive/20251028/202510281329.racaZPSI-lkp@intel.com/config) > > > compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 > > > reproduce (this is a W=3D1 build): (https://download.01.org/0day-ci/a= rchive/20251028/202510281329.racaZPSI-lkp@intel.com/reproduce) > > >=20 > > > If you fix the issue in a separate patch/commit (i.e. not just a new = version of > > > the same patch/commit), kindly add following tags > > > > Reported-by: kernel test robot > > > > Closes: https://lore.kernel.org/oe-kbuild-all/202510281329.racaZPSI= -lkp@intel.com/ > > >=20 > > > All warnings (new ones prefixed by >>): > > >=20 > > > drivers/pci/controller/cadence/pcie-cadence-host.c: In function 'c= dns_pcie_setup_lane_equalization_presets': > > > > > drivers/pci/controller/cadence/pcie-cadence-host.c:205:20: warnin= g: this statement may fall through [-Wimplicit-fallthrough=3D] > > > 205 | if (presets_ngts[0] !=3D PCI_EQ_RESV) { > > > | ^ > > > drivers/pci/controller/cadence/pcie-cadence-host.c:225:9: note: he= re > > > 225 | case PCIE_SPEED_8_0GT: > > > | ^~~~ > >=20 > > Fallthrough is intentional. The lane equalization presets are programme= d > > starting from the Max Supported Link speed and we fallthrough until we = get > > to 8.0 GT/s. >=20 > It's poorly documented, but use "fallthrough" here: >=20 > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/D= ocumentation/process/deprecated.rst?id=3Dv6.17#n200 Thank you for pointing me to the documentation. I will update the patch accordingly and post the v2 patch. Regards, Siddharth.