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Sun, 21 Dec 2025 22:51:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IGTvgv1hHER1oJ5VEZI/LUm+x0Rgz+j+dmzfrj2FJyfQHSPSjcRw6dQUbfv/KXkbw7LePCVTA== X-Received: by 2002:a17:902:be0a:b0:2a0:e5da:febf with SMTP id d9443c01a7336-2a2f283de4bmr63910805ad.46.1766386281921; Sun, 21 Dec 2025 22:51:21 -0800 (PST) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2a2f3c66932sm88235205ad.11.2025.12.21.22.51.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 21 Dec 2025 22:51:21 -0800 (PST) Message-ID: Date: Mon, 22 Dec 2025 12:21:16 +0530 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/6] Revert "PCI: qcom: Enumerate endpoints based on Link up event in 'global_irq' interrupt" To: Niklas Cassel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: Shawn Lin , FUKAUMI Naoki , Krishna chaitanya chundru , Damien Le Moal , stable@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20251222064207.3246632-8-cassel@kernel.org> <20251222064207.3246632-13-cassel@kernel.org> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: <20251222064207.3246632-13-cassel@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjIyMDA2MCBTYWx0ZWRfX09yg5jduBwRy asnxmJdn2CuL3+vHIFUx3xVnXsveMVd/Vw3TSdQ538X1RNn03XyGVc/G4InA5CwfwMnI/Pe/Nhi oFTntTQZ8j7c/7x4N39hnr0YmVJgduqMbfjnEHClWF9gcZIocgGCzhwUHk367TTPYOqhuL6HNYO nc1PI440vCKdTmwJ3gA5sn6CmvaHP3xQfBvDO1b2aFBsfk7+KKFyu1PBwuJ/GMQ5xirz2DZurNP eF/y08xxJS/KvfW6k7uW5cuPPscvKeSS7dh3ufWb/mIUFnPcO9tMzGMqWdGF0TXn43U4STB8MBL zy/tMoAbfzYTy6OHlH9NpovZ3HUV2m0cDZX6A/Dtd94sUeDMIpcCuUkLDsjxOpI6PefCR+0KWle CT0iH/RYxw0+2USRtUaNNiFoOtF5xrnA4z0fV+OqAB2J2YKeLJmXOv4KValidazkmDg6B+8hqGF 7My8G/Tq8YNA+K/LBug== X-Proofpoint-GUID: HZVvfKdRzC1Nvkjqfl3EgujrvcJORpUb X-Proofpoint-ORIG-GUID: HZVvfKdRzC1Nvkjqfl3EgujrvcJORpUb X-Authority-Analysis: v=2.4 cv=KYbfcAYD c=1 sm=1 tr=0 ts=6948ea6b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=VwQbUJbxAAAA:8 a=s8YR1HE3AAAA:8 a=gPGEdhGqammTKEiSqskA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=jGH_LyMDp9YhSvY-UuyI:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-21_05,2025-12-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512220060 On 12/22/2025 12:12 PM, Niklas Cassel wrote: > This reverts commit 4581403f67929d02c197cb187c4e1e811c9e762a. > > While this fake hotplugging was a nice idea, it has shown that this feature > does not handle PCIe switches correctly: > pci_bus 0004:43: busn_res: can not insert [bus 43-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:43: busn_res: [bus 43-41] end is updated to 43 > pci_bus 0004:43: busn_res: can not insert [bus 43] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:00.0: devices behind bridge are unusable because [bus 43] cannot be assigned for them > pci_bus 0004:44: busn_res: can not insert [bus 44-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:44: busn_res: [bus 44-41] end is updated to 44 > pci_bus 0004:44: busn_res: can not insert [bus 44] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:02.0: devices behind bridge are unusable because [bus 44] cannot be assigned for them > pci_bus 0004:45: busn_res: can not insert [bus 45-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:45: busn_res: [bus 45-41] end is updated to 45 > pci_bus 0004:45: busn_res: can not insert [bus 45] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:06.0: devices behind bridge are unusable because [bus 45] cannot be assigned for them > pci_bus 0004:46: busn_res: can not insert [bus 46-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci_bus 0004:46: busn_res: [bus 46-41] end is updated to 46 > pci_bus 0004:46: busn_res: can not insert [bus 46] under [bus 42-41] (conflicts with (null) [bus 42-41]) > pci 0004:42:0e.0: devices behind bridge are unusable because [bus 46] cannot be assigned for them > pci_bus 0004:42: busn_res: [bus 42-41] end is updated to 46 > pci_bus 0004:42: busn_res: can not insert [bus 42-46] under [bus 41] (conflicts with (null) [bus 41]) > pci 0004:41:00.0: devices behind bridge are unusable because [bus 42-46] cannot be assigned for them > pcieport 0004:40:00.0: bridge has subordinate 41 but max busn 46 > > During the initial scan, PCI core doesn't see the switch and since the Root > Port is not hot plug capable, the secondary bus number gets assigned as the > subordinate bus number. This means, the PCI core assumes that only one bus > will appear behind the Root Port since the Root Port is not hot plug > capable. > > This works perfectly fine for PCIe endpoints connected to the Root Port, > since they don't extend the bus. However, if a PCIe switch is connected, > then there is a problem when the downstream busses starts showing up and > the PCI core doesn't extend the subordinate bus number after initial scan > during boot. > > The long term plan is to migrate this driver to the pwrctrl framework, > once it adds proper support for powering up and enumerating PCIe switches. > > Cc: stable@vger.kernel.org > Suggested-by: Manivannan Sadhasivam > Acked-by: Shawn Lin > Tested-by: Shawn Lin > Signed-off-by: Niklas Cassel Removing patch 3/6 should be sufficient, don't remove global IRQ patch, this will be helpful when endpoint is connected at later point of time. - Krishna Chaitanya. > --- > drivers/pci/controller/dwc/pcie-qcom.c | 58 +------------------------- > 1 file changed, 1 insertion(+), 57 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index c5fcb87972e9..13e6c334e10d 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -55,9 +55,6 @@ > #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 > #define PARF_Q2A_FLUSH 0x1ac > #define PARF_LTSSM 0x1b0 > -#define PARF_INT_ALL_STATUS 0x224 > -#define PARF_INT_ALL_CLEAR 0x228 > -#define PARF_INT_ALL_MASK 0x22c > #define PARF_SID_OFFSET 0x234 > #define PARF_BDF_TRANSLATE_CFG 0x24c > #define PARF_DBI_BASE_ADDR_V2 0x350 > @@ -134,9 +131,6 @@ > /* PARF_LTSSM register fields */ > #define LTSSM_EN BIT(8) > > -/* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ > -#define PARF_INT_ALL_LINK_UP BIT(13) > - > /* PARF_NO_SNOOP_OVERRIDE register fields */ > #define WR_NO_SNOOP_OVERRIDE_EN BIT(1) > #define RD_NO_SNOOP_OVERRIDE_EN BIT(3) > @@ -1635,32 +1629,6 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) > qcom_pcie_link_transition_count); > } > > -static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data) > -{ > - struct qcom_pcie *pcie = data; > - struct dw_pcie_rp *pp = &pcie->pci->pp; > - struct device *dev = pcie->pci->dev; > - u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS); > - > - writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR); > - > - if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) { > - msleep(PCIE_RESET_CONFIG_WAIT_MS); > - dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); > - /* Rescan the bus to enumerate endpoint devices */ > - pci_lock_rescan_remove(); > - pci_rescan_bus(pp->bridge->bus); > - pci_unlock_rescan_remove(); > - > - qcom_pcie_icc_opp_update(pcie); > - } else { > - dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n", > - status); > - } > - > - return IRQ_HANDLED; > -} > - > static void qcom_pci_free_msi(void *ptr) > { > struct dw_pcie_rp *pp = (struct dw_pcie_rp *)ptr; > @@ -1805,8 +1773,7 @@ static int qcom_pcie_probe(struct platform_device *pdev) > struct dw_pcie_rp *pp; > struct resource *res; > struct dw_pcie *pci; > - int ret, irq; > - char *name; > + int ret; > > pcie_cfg = of_device_get_match_data(dev); > if (!pcie_cfg) { > @@ -1963,27 +1930,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) > goto err_phy_exit; > } > > - name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d", > - pci_domain_nr(pp->bridge->bus)); > - if (!name) { > - ret = -ENOMEM; > - goto err_host_deinit; > - } > - > - irq = platform_get_irq_byname_optional(pdev, "global"); > - if (irq > 0) { > - ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, > - qcom_pcie_global_irq_thread, > - IRQF_ONESHOT, name, pcie); > - if (ret) { > - dev_err_probe(&pdev->dev, ret, > - "Failed to request Global IRQ\n"); > - goto err_host_deinit; > - } > - > - writel_relaxed(PARF_INT_ALL_LINK_UP, pcie->parf + PARF_INT_ALL_MASK); > - } > - > qcom_pcie_icc_opp_update(pcie); > > if (pcie->mhi) > @@ -1991,8 +1937,6 @@ static int qcom_pcie_probe(struct platform_device *pdev) > > return 0; > > -err_host_deinit: > - dw_pcie_host_deinit(pp); > err_phy_exit: > list_for_each_entry_safe(port, tmp, &pcie->ports, list) { > phy_exit(port->phy);