From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A35ABC4332F for ; Mon, 6 Nov 2023 08:24:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229785AbjKFIYE (ORCPT ); Mon, 6 Nov 2023 03:24:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbjKFIYD (ORCPT ); Mon, 6 Nov 2023 03:24:03 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 266CBB0; Mon, 6 Nov 2023 00:24:01 -0800 (PST) Received: from [100.107.97.3] (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id C0EAC660746C; Mon, 6 Nov 2023 08:23:58 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1699259039; bh=xO8B0RTmTlne22NX2ar9sHfGqtBP8hpPG2QaQgD8NXc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=D/QFoBxdbIiGmwc50U0NKIBIQc3PG7WMxvICc5qFMMRoQmeA4501FUrmVpanBsjKs hfAQsfXraDHMCI5uiWB7ai/tIta/dauK9oG4R9SgAyeRFWkUgsmu0hvRP64MHwPD6V ajc1ddAL0AfvKAKEILTQrl5zjz+kQT2wN97ylQZ2+yb9bCsqECPk3fPrCWulXCGouo vr8h+mocO4sf0sPPozh3fG9PXYcKeK39iXxEnvzo5uirI5zN2VX96i21V9SIIJOMIv IuAn/+Rfn/DY9t0mW2Qx9VWOWRwhrAqAGVTbKHAZnXuhrflNXZEzTo6P9dkTtiP0dJ CDqlzAImtPI+A== Message-ID: Date: Mon, 6 Nov 2023 09:23:55 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 2/2] PCI: mediatek-gen3: Add power and reset control feature for downstream component Content-Language: en-US To: Jian Yang , Bjorn Helgaas , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Lorenzo Pieralisi , Matthias Brugger , Rob Herring , Jianjun Wang Cc: linux-pci@vger.kernel.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com, Chuanjia.Liu@mediatek.com, Jieyy.Yang@mediatek.com, Qizhong.Cheng@mediatek.com, Jianguo.Zhang@mediatek.com References: <20231106061220.21485-1-jian.yang@mediatek.com> <20231106061220.21485-3-jian.yang@mediatek.com> From: AngeloGioacchino Del Regno In-Reply-To: <20231106061220.21485-3-jian.yang@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Il 06/11/23 07:12, Jian Yang ha scritto: > From: "jian.yang" > > Make MediaTek's controller driver capable of controlling power > supplies and reset pin of a downstream component in power-on and > power-off process. > > Some downstream components (e.g., a WIFI chip) may need an extra > reset other than PERST# and their power supplies, depending on > the requirements of platform, may need to controlled by their > parent's driver. To meet the requirements described above, I add this > feature to MediaTek's PCIe controller driver as an optional feature. > > Signed-off-by: jian.yang Reviewed-by: AngeloGioacchino Del Regno