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From: "Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
To: Val Packett <val@packett.cool>
Cc: linux-pci@vger.kernel.org, "Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"Lucas De Marchi" <lucas.demarchi@intel.com>
Subject: Re: [PATCH 1/2] PCI: Setup bridge resources earlier
Date: Mon, 6 Oct 2025 13:46:54 +0300 (EEST)	[thread overview]
Message-ID: <f5eb0360-55bd-723c-eca2-b0f7d8971848@linux.intel.com> (raw)
In-Reply-To: <017ff8df-511c-4da8-b3cf-edf2cb7f1a67@packett.cool>

[-- Attachment #1: Type: text/plain, Size: 5365 bytes --]

On Mon, 6 Oct 2025, Val Packett wrote:
> On 9/24/25 10:42 AM, Ilpo Järvinen wrote:
> > Bridge windows are read twice from PCI Config Space, the first read is
> > made from pci_read_bridge_windows() which does not setup the device's
> > resources. It causes problems down the road as child resources of the
> > bridge cannot check whether they reside within the bridge window or
> > not.
> > 
> > Setup the bridge windows already in pci_read_bridge_windows().
> > 
> > Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
> 
> Looks like this change has broken the WiFi (but not NVMe) on my Snapdragon X1E
> laptop (Latitude 7455):

Thanks for the report.

> qcom-pcie 1c08000.pci: PCI host bridge to bus 0004:00
> pci_bus 0004:00: root bus resource [bus 00-ff]
> pci_bus 0004:00: root bus resource [io  0x100000-0x1fffff] (bus address [0x0000-0xfffff])

So this looks the first change visible in the fragment you've taken from 
the dmesg...

> pci_bus 0004:00: root bus resource [mem 0x7c300000-0x7dffffff]
> pci 0004:00:00.0: [17cb:0111] type 01 class 0x060400 PCIe Root Port
> pci 0004:00:00.0: BAR 0 [mem 0x00000000-0x00000fff]
> pci 0004:00:00.0: PCI bridge to [bus 01-ff]

...What I don't understand in these logs is how can the code changed in 
pci_read_bridge_windows() affect the lines before this line as it is being 
printed from pci_read_bridge_windows(). Maybe there are more 'PCI bridge 
to' lines above the quoted part of the dmesg?

> pci 0004:00:00.0:   bridge window [io  0x100000-0x100fff]
> pci 0004:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
> pci 0004:00:00.0:   bridge window [mem 0x00000000-0x000fffff 64bit pref]
> pci 0004:00:00.0: PME# supported from D0 D3hot D3cold
> pci 0004:00:00.0: bridge window [mem 0x7c300000-0x7c3fffff]: assigned
> pci 0004:00:00.0: bridge window [mem 0x7c400000-0x7c4fffff 64bit pref]: assigned
> pci 0004:00:00.0: BAR 0 [mem 0x7c500000-0x7c500fff]: assigned
> pci 0004:00:00.0: bridge window [io  0x100000-0x100fff]: assigned
> pci 0004:00:00.0: PCI bridge to [bus 01-ff]
> pci 0004:00:00.0:   bridge window [io  0x100000-0x100fff]
> pci 0004:00:00.0:   bridge window [mem 0x7c300000-0x7c3fffff]
> pci 0004:00:00.0:   bridge window [mem 0x7c400000-0x7c4fffff 64bit pref]
> pci_bus 0004:00: resource 4 [io  0x100000-0x1fffff]
> pci_bus 0004:00: resource 5 [mem 0x7c300000-0x7dffffff]
> pci_bus 0004:01: resource 0 [io  0x100000-0x100fff]
> pci_bus 0004:01: resource 1 [mem 0x7c300000-0x7c3fffff]
> pci_bus 0004:01: resource 2 [mem 0x7c400000-0x7c4fffff 64bit pref]
> pcieport 0004:00:00.0: PME: Signaling with IRQ 186
> pcieport 0004:00:00.0: AER: enabled with IRQ 186
> pci 0004:01:00.0: [17cb:1107] type 00 class 0x028000 PCIe Endpoint
> pci 0004:01:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> pci 0004:01:00.0: PME# supported from D0 D3hot D3cold
> pci 0004:01:00.0: BAR 0 [mem size 0x00200000 64bit]: can't assign; no space
> pci 0004:01:00.0: BAR 0 [mem size 0x00200000 64bit]: failed to assign
> pci 0004:01:00.0: BAR 0 [mem size 0x00200000 64bit]: can't assign; no space
> pci 0004:01:00.0: BAR 0 [mem size 0x00200000 64bit]: failed to assign
> ath12k_pci 0004:01:00.0: BAR 0 [??? 0x00000000 flags 0x20000000]: can't
> assign; bogus alignment
> ath12k_pci 0004:01:00.0: failed to assign pci resource: -22
> ath12k_pci 0004:01:00.0: failed to claim device: -22
> ath12k_pci 0004:01:00.0: probe with driver ath12k_pci failed with error -22
> 
> 
> For comparison, with this change reverted it works again:
> 
> qcom-pcie 1c08000.pci: PCI host bridge to bus 0004:00
> pci_bus 0004:00: root bus resource [bus 00-ff]
> pci_bus 0004:00: root bus resource [io  0x0000-0xfffff]
> pci_bus 0004:00: root bus resource [mem 0x7c300000-0x7dffffff]
> pci 0004:00:00.0: [17cb:0111] type 01 class 0x060400 PCIe Root Port
> pci 0004:00:00.0: BAR 0 [mem 0x00000000-0x00000fff]
> pci 0004:00:00.0: PCI bridge to [bus 01-ff]
> pci 0004:00:00.0:   bridge window [io  0x0000-0x0fff]
> pci 0004:00:00.0:   bridge window [mem 0x00000000-0x000fffff]
> pci 0004:00:00.0:   bridge window [mem 0x00000000-0x000fffff 64bit pref]
> pci 0004:00:00.0: PME# supported from D0 D3hot D3cold
> pci 0004:00:00.0: BAR 0 [mem 0x7c300000-0x7c300fff]: assigned
> pci 0004:00:00.0: PCI bridge to [bus 01-ff]
> pci_bus 0004:00: resource 4 [io  0x0000-0xfffff]
> pci_bus 0004:00: resource 5 [mem 0x7c300000-0x7dffffff]
> pcieport 0004:00:00.0: PME: Signaling with IRQ 195
> pcieport 0004:00:00.0: AER: enabled with IRQ 195
> pci 0004:01:00.0: [17cb:1107] type 00 class 0x028000 PCIe Endpoint
> pci 0004:01:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> pci 0004:01:00.0: PME# supported from D0 D3hot D3cold
> pci 0004:01:00.0: ASPM: DT platform, enabling L0s-up L0s-dw L1 ASPM-L1.1
> ASPM-L1.2 PCI-PM-L1.1 PCI-PM-L1.2
> pci 0004:01:00.0: ASPM: DT platform, enabling ClockPM
> pcieport 0004:00:00.0: bridge window [mem 0x7c400000-0x7c5fffff]: assigned
> pci 0004:01:00.0: BAR 0 [mem 0x7c400000-0x7c5fffff 64bit]: assigned
> ath12k_pci 0004:01:00.0: BAR 0 [mem 0x7c400000-0x7c5fffff 64bit]: assigned
> ath12k_pci 0004:01:00.0: enabling device (0000 -> 0002)
> ath12k_pci 0004:01:00.0: MSI vectors: 16
> ath12k_pci 0004:01:00.0: Hardware name: wcn7850 hw2.0
> 
> Not quite sure what's going on with these windows..



-- 
 i.

  reply	other threads:[~2025-10-06 10:47 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-24 13:42 [PATCH 0/2] PCI: Fix bogus resource overlaps Ilpo Järvinen
2025-09-24 13:42 ` [PATCH 1/2] PCI: Setup bridge resources earlier Ilpo Järvinen
2025-10-06  8:00   ` Val Packett
2025-10-06 10:46     ` Ilpo Järvinen [this message]
2025-10-06 20:08       ` Val Packett
2025-10-07 15:43         ` Ilpo Järvinen
2025-10-09  7:29           ` Val Packett
2025-10-10 17:01             ` Ilpo Järvinen
2025-10-12  6:29               ` Val Packett
2025-10-16  7:42           ` Manivannan Sadhasivam
2025-10-13 21:01     ` Bjorn Helgaas
2025-10-28 22:47       ` Bjorn Helgaas
2025-10-30 22:08         ` Bjorn Helgaas
2025-10-13 18:07   ` Guenter Roeck
2025-10-14 11:20     ` Ilpo Järvinen
2025-10-17 18:22   ` Bhanu Seshu Kumar Valluri
2025-10-17 18:27     ` Bhanu Seshu Kumar Valluri
2025-10-17 18:52     ` Bjorn Helgaas
2025-10-18  1:57       ` Bhanu Seshu Kumar Valluri
2025-10-20 18:46         ` Ilpo Järvinen
2025-10-27  8:10           ` Bhanu Seshu Kumar Valluri
2025-10-27 13:49             ` Ilpo Järvinen
2025-09-24 13:42 ` [PATCH 2/2] PCI: Resources outside their window must set IORESOURCE_UNSET Ilpo Järvinen
2025-09-25 21:21   ` Bjorn Helgaas
2025-09-26 12:21     ` Ilpo Järvinen
2025-09-26 19:30       ` Bjorn Helgaas
2025-09-29 10:34         ` Ilpo Järvinen
2025-09-30 15:47   ` Geert Uytterhoeven
2025-09-30 16:32     ` Ilpo Järvinen
2025-10-01 11:49       ` Geert Uytterhoeven
2025-10-01 13:06         ` Ilpo Järvinen
2025-10-01 14:08           ` Geert Uytterhoeven
2025-10-02 14:54             ` Ilpo Järvinen
2025-10-02 15:25               ` Geert Uytterhoeven
2025-10-02 16:59                 ` Ilpo Järvinen
2025-10-03  8:36                   ` Geert Uytterhoeven
2025-10-03 14:58                     ` Ilpo Järvinen
2025-10-06 10:14                       ` Geert Uytterhoeven
2025-10-06 12:37                         ` Ilpo Järvinen
2025-10-06 13:17                           ` Geert Uytterhoeven
2025-10-07 17:30                             ` Ilpo Järvinen
2025-10-08  8:40                               ` Kai-Heng Feng
2025-10-08 13:57                               ` Geert Uytterhoeven
2025-09-24 23:48 ` [PATCH 0/2] PCI: Fix bogus resource overlaps Bjorn Helgaas

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