From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF3F5C04AB4 for ; Tue, 21 May 2019 16:47:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B2F22217D7 for ; Tue, 21 May 2019 16:47:40 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="EeQpa9fi" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728256AbfEUQrg (ORCPT ); Tue, 21 May 2019 12:47:36 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:1173 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727965AbfEUQrg (ORCPT ); Tue, 21 May 2019 12:47:36 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 21 May 2019 09:47:35 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 21 May 2019 09:47:34 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 21 May 2019 09:47:34 -0700 Received: from [10.25.72.115] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 21 May 2019 16:47:29 +0000 Subject: Re: [PATCH V7 02/15] PCI: Disable MSI for Tegra194 root port To: Thierry Reding CC: , , , , , , , , , , , , , , , , , , References: <20190517123846.3708-1-vidyas@nvidia.com> <20190517123846.3708-3-vidyas@nvidia.com> <20190521102729.GB29166@ulmo> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Tue, 21 May 2019 22:17:26 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190521102729.GB29166@ulmo> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL103.nvidia.com (172.20.187.11) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1558457255; bh=BlKoVyxfa3/PhGnDYxQwviA1iVDUS1wMLF49XD5WLTo=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=EeQpa9fitk/OpoQb5fgRexaj/4U0V03Hh0lFLdmYSKWSxWr0BxeUY1pOsh3perPWB SVrQaG2Es6cVEJE9EcAkpzaUoe60SPjdpXy08bnbbNt9SXoNgvTk4Zh9/BoEqEtNSW NPLtiibkt0oh3/H2R3pz2t8h0xyFRQ0W9hxD4848k7pI4sY8vWFWGltTlk8aT8G5wQ NdeLJpPeJqt0Z9aq2LNe77mtwWiM3EwVsYl7NZCFrZfxwU0pFW6XX/hp7Cet/gZsnm yjcGWIB56i2lBnp8u4z42Li1AYeei5ZBUCmPodnipCn0mPZNdyRypL1GmUo5PaUvx8 /rRw7QYrXZMww== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 5/21/2019 3:57 PM, Thierry Reding wrote: > On Fri, May 17, 2019 at 06:08:33PM +0530, Vidya Sagar wrote: >> Tegra194 rootports don't generate MSI interrupts for PME events and hence >> MSI needs to be disabled for them to avoid root ports service drivers >> registering their respective ISRs with MSI interrupt. >> >> Signed-off-by: Vidya Sagar >> --- >> Changes since [v6]: >> * This is a new patch >> >> drivers/pci/quirks.c | 14 ++++++++++++++ >> 1 file changed, 14 insertions(+) >> >> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c >> index 0f16acc323c6..28f9a0380df5 100644 >> --- a/drivers/pci/quirks.c >> +++ b/drivers/pci/quirks.c >> @@ -2592,6 +2592,20 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, >> PCI_DEVICE_ID_NVIDIA_NVENET_15, >> nvenet_msi_disable); >> >> +/* >> + * Tegra194's PCIe root ports don't generate MSI interrupts for PME events >> + * instead legacy interrupts are generated. Hence, to avoid service drivers >> + * registering their respective ISRs for MSIs, need to disable MSI interrupts >> + * for root ports. >> + */ >> +static void disable_tegra194_rp_msi(struct pci_dev *dev) >> +{ >> + dev->no_msi = 1; >> +} >> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, disable_tegra194_rp_msi); >> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, disable_tegra194_rp_msi); >> +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, disable_tegra194_rp_msi); >> + > > Later functions in this file seem to use a more consistent naming > pattern, according to which the name for this would become: > > pci_quirk_nvidia_tegra194_disable_rp_msi > > Might be worth considering making this consistent. > > This could also be moved to the DWC driver to restrict this to where it > is needed. In either case, this seems like a good solution, so: > > Reviewed-by: Thierry Reding > Ok. I'll move it to DWC driver along with name change for the quirk API.