Re: [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts

[Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>]

On 28/04/2022 16:45, Dmitry Baryshkov wrote:
> On 28/04/2022 17:06, Krzysztof Kozlowski wrote:
>> On 28/04/2022 15:57, Dmitry Baryshkov wrote:
>>> On Thu, 28 Apr 2022 at 15:08, Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 28/04/2022 13:59, Dmitry Baryshkov wrote:
>>>>> On Qualcomm platforms each group of 32 MSI vectors is routed to the
>>>>> separate GIC interrupt. Document mapping of additional interrupts.
>>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>>   .../devicetree/bindings/pci/qcom,pcie.yaml    | 51 ++++++++++++++++++-
>>>>>   1 file changed, 50 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>> index 0b69b12b849e..a8f99bca389e 100644
>>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml
>>>>> @@ -43,11 +43,20 @@ properties:
>>>>>       maxItems: 5
>>>>>
>>>>>     interrupts:
>>>>> -    maxItems: 1
>>>>> +    minItems: 1
>>>>> +    maxItems: 8
>>>>>
>>>>>     interrupt-names:
>>>>> +    minItems: 1
>>>>>       items:
>>>>>         - const: msi
>>>>> +      - const: msi2
>>>>> +      - const: msi3
>>>>> +      - const: msi4
>>>>> +      - const: msi5
>>>>> +      - const: msi6
>>>>> +      - const: msi7
>>>>> +      - const: msi8
>>>>>
>>>>>     # Common definitions for clocks, clock-names and reset.
>>>>>     # Platform constraints are described later.
>>>>> @@ -623,6 +632,46 @@ allOf:
>>>>>           - resets
>>>>>           - reset-names
>>>>>
>>>>> +    # On newer chipsets support either 1 or 8 msi interrupts
>>>>> +    # On older chipsets it's always 1 msi interrupt
>>>>> +  - if:
>>>>> +      properties:
>>>>> +        compatibles:
>>>>> +          contains:
>>>>> +            enum:
>>>>> +              - qcom,pcie-msm8996
>>>>> +              - qcom,pcie-sc7280
>>>>> +              - qcom,pcie-sc8180x
>>>>> +              - qcom,pcie-sdm845
>>>>> +              - qcom,pcie-sm8150
>>>>> +              - qcom,pcie-sm8250
>>>>> +              - qcom,pcie-sm8450-pcie0
>>>>> +              - qcom,pcie-sm8450-pcie1
>>>>> +    then:
>>>>> +      oneOf:
>>>>> +        - properties:
>>>>> +            interrupts:
>>>>> +              minItems: 1
>>>>
>>>> minItems should not be needed here and in places below, because it is
>>>> equal to maxItems.
>>>
>>> Maybe it's a misunderstanding from my side. In the top level we have
>>> the min = 1, max = 8.
>>> How does that interfere with these entries? In other words, if we e.g.
>>> omit minItems here, which setting would preveal: implicit minItems = 8
>>> (from maxItems = 8) or minItems = 1 in the top level?
>>>
>>>>> +              maxItems: 1
>>
>> I don't propose to skip it for the case with maxItems:8, but only here.
>> minItems:1 is set in toplevel. Where is that implicit minItems:8?
> 
> maxItems:8? Maybe I just misunderstand this part of yaml/jsonschema.

The top level defines minItems=1, maxItems=8, so it cannot mean
implicitly "minItems=1, maxItems=8, minItems=maxItems".

There is no other place in the bindings which would implicitly set here
minItems=maxItems.


Best regards,
Krzysztof