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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id v3-20020aa7d9c3000000b0042617ba63cesm2592560eds.88.2022.04.28.23.49.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Apr 2022 23:49:17 -0700 (PDT) Message-ID: Date: Fri, 29 Apr 2022 08:49:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH v4 6/7] dt-bindings: pci/qcom,pcie: support additional MSI interrupts Content-Language: en-US To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Rob Herring , Jingoo Han , Gustavo Pimentel , Lorenzo Pieralisi , Bjorn Helgaas , Stanimir Varbanov , Manivannan Sadhasivam , Vinod Koul , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org References: <20220428115934.3414641-1-dmitry.baryshkov@linaro.org> <20220428115934.3414641-7-dmitry.baryshkov@linaro.org> <6bd8eb4e-81eb-7e87-155b-f48b487e16ae@linaro.org> <42588c32-5068-5f12-4cf8-f8b9bd074e88@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 28/04/2022 16:45, Dmitry Baryshkov wrote: > On 28/04/2022 17:06, Krzysztof Kozlowski wrote: >> On 28/04/2022 15:57, Dmitry Baryshkov wrote: >>> On Thu, 28 Apr 2022 at 15:08, Krzysztof Kozlowski >>> wrote: >>>> >>>> On 28/04/2022 13:59, Dmitry Baryshkov wrote: >>>>> On Qualcomm platforms each group of 32 MSI vectors is routed to the >>>>> separate GIC interrupt. Document mapping of additional interrupts. >>>>> >>>>> Signed-off-by: Dmitry Baryshkov >>>>> --- >>>>> .../devicetree/bindings/pci/qcom,pcie.yaml | 51 ++++++++++++++++++- >>>>> 1 file changed, 50 insertions(+), 1 deletion(-) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>>>> index 0b69b12b849e..a8f99bca389e 100644 >>>>> --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>>>> +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml >>>>> @@ -43,11 +43,20 @@ properties: >>>>> maxItems: 5 >>>>> >>>>> interrupts: >>>>> - maxItems: 1 >>>>> + minItems: 1 >>>>> + maxItems: 8 >>>>> >>>>> interrupt-names: >>>>> + minItems: 1 >>>>> items: >>>>> - const: msi >>>>> + - const: msi2 >>>>> + - const: msi3 >>>>> + - const: msi4 >>>>> + - const: msi5 >>>>> + - const: msi6 >>>>> + - const: msi7 >>>>> + - const: msi8 >>>>> >>>>> # Common definitions for clocks, clock-names and reset. >>>>> # Platform constraints are described later. >>>>> @@ -623,6 +632,46 @@ allOf: >>>>> - resets >>>>> - reset-names >>>>> >>>>> + # On newer chipsets support either 1 or 8 msi interrupts >>>>> + # On older chipsets it's always 1 msi interrupt >>>>> + - if: >>>>> + properties: >>>>> + compatibles: >>>>> + contains: >>>>> + enum: >>>>> + - qcom,pcie-msm8996 >>>>> + - qcom,pcie-sc7280 >>>>> + - qcom,pcie-sc8180x >>>>> + - qcom,pcie-sdm845 >>>>> + - qcom,pcie-sm8150 >>>>> + - qcom,pcie-sm8250 >>>>> + - qcom,pcie-sm8450-pcie0 >>>>> + - qcom,pcie-sm8450-pcie1 >>>>> + then: >>>>> + oneOf: >>>>> + - properties: >>>>> + interrupts: >>>>> + minItems: 1 >>>> >>>> minItems should not be needed here and in places below, because it is >>>> equal to maxItems. >>> >>> Maybe it's a misunderstanding from my side. In the top level we have >>> the min = 1, max = 8. >>> How does that interfere with these entries? In other words, if we e.g. >>> omit minItems here, which setting would preveal: implicit minItems = 8 >>> (from maxItems = 8) or minItems = 1 in the top level? >>> >>>>> + maxItems: 1 >> >> I don't propose to skip it for the case with maxItems:8, but only here. >> minItems:1 is set in toplevel. Where is that implicit minItems:8? > > maxItems:8? Maybe I just misunderstand this part of yaml/jsonschema. The top level defines minItems=1, maxItems=8, so it cannot mean implicitly "minItems=1, maxItems=8, minItems=maxItems". There is no other place in the bindings which would implicitly set here minItems=maxItems. Best regards, Krzysztof