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Fri, 9 May 2025 01:53:52 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: Tfcfb78bcf68431d5 Date: Fri, 09 May 2025 07:53:31 +0200 From: "Arnd Bergmann" To: "Andrew Ballance" , "Danilo Krummrich" , "Dave Airlie" , "Simona Vetter" , "Andrew Morton" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "Greg Kroah-Hartman" , "Rafael J . Wysocki" , bhelgaas@google.com, =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , "Raag Jadav" , "Andy Shevchenko" , me@kloenk.dev, "FUJITA Tomonori" , daniel.almeida@collabora.com Cc: "nouveau@lists.freedesktop.org" , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-pci@vger.kernel.org Message-Id: In-Reply-To: <20250509031524.2604087-1-andrewjballance@gmail.com> References: <20250509031524.2604087-1-andrewjballance@gmail.com> Subject: Re: [PATCH 00/11] rust: add support for Port io Content-Type: text/plain Content-Transfer-Encoding: 7bit On Fri, May 9, 2025, at 05:15, Andrew Ballance wrote: > currently the rust `Io` type maps to the c read{b, w, l, q}/write{b, w, l, q} > functions and have no support for port io.this is a problem for pci::Bar > because the pointer returned by pci_iomap is expected to accessed with > the ioread/iowrite api [0]. > > this patch series splits the `Io` type into `Io`, `PortIo` and `MMIo`.and, > updates pci::Bar, as suggested in the zulip[1], so that it is generic over > Io and, a user can optionally give a compile time hint about the type of io. Can you describe here why you want to support both "Io" and "PortIo" cases separately? I don't think we need to micro-optimize for legacy ISA devices any more, so I'd hope the "Io" path would be sufficient to cover the common outliers (ata, uart, vga, ipmi, ne2000) that need the iomap indirection and also the legacy devices that only need port I/O (floppy, x86 platform devices, ...). Ideally we'd only need one set of I/O accessors at all, but I suspect there are x86 specific drivers that actually need readl/writel to be inline for performance when accessing on-chip registers rather than slow PCIe registers. Arnd