From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71437C282CE for ; Wed, 22 May 2019 09:00:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 468C0217D4 for ; Wed, 22 May 2019 09:00:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="KEGjkhgZ" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728743AbfEVI7z (ORCPT ); Wed, 22 May 2019 04:59:55 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:15362 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728406AbfEVI7z (ORCPT ); Wed, 22 May 2019 04:59:55 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Wed, 22 May 2019 01:59:54 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 22 May 2019 01:59:54 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 22 May 2019 01:59:54 -0700 Received: from [10.24.45.128] (172.20.13.39) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 22 May 2019 08:59:49 +0000 Subject: Re: [PATCH V7 13/15] phy: tegra: Add PCIe PIPE2UPHY support To: Thierry Reding CC: , , , , , , , , , , , , , , , , , , References: <20190517123846.3708-1-vidyas@nvidia.com> <20190517123846.3708-14-vidyas@nvidia.com> <20190521110053.GM29166@ulmo> X-Nvconfidentiality: public From: Vidya Sagar Message-ID: Date: Wed, 22 May 2019 14:29:46 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 In-Reply-To: <20190521110053.GM29166@ulmo> X-Originating-IP: [172.20.13.39] X-ClientProxiedBy: HQMAIL106.nvidia.com (172.18.146.12) To HQMAIL107.nvidia.com (172.20.187.13) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1558515594; bh=j8nUL7CYBN3ZSo9bQt9cG2C16yOUGsDVML131j+TReM=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=KEGjkhgZ4IGYiJr81sxvF7ROIJV5hZOAAAyoNOT3N3R64IL1IjiYpe1e7a2VMGAp+ gDcBbDCRMD6xj52cZGirkKwtyaQKp2u15PVY5TfCDAB6efYwHK5WGu462lxpFfa7jD U17xB8s8C1XcbW1hs4Hp7nJDoYkuGrr/PxLVEoASViQrk5993GSteP7uqtiZlUAkFe oDh4Qroc/slfkPKFkGBGn7DERLLWki7GYkkM1O2ayFbLZcHv4fjuI4hjnYllCQxdvB ee+4uhzcUsk7KtsYIEe1CsYgwxHXF1aAJPgfN4QvaclgbJFOQd1mk9uEk4WDkvwbGw 14JY5mSLixK4A== Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 5/21/2019 4:30 PM, Thierry Reding wrote: > On Fri, May 17, 2019 at 06:08:44PM +0530, Vidya Sagar wrote: >> Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface >> with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module. >> For each PCIe lane of a controller, there is a P2U unit instantiated at >> hardware level. This driver provides support for the programming required >> for each P2U that is going to be used for a PCIe controller. >> >> Signed-off-by: Vidya Sagar >> --- >> Changes since [v6]: >> * None >> >> Changes since [v5]: >> * Addressed review comments from Thierry >> >> Changes since [v4]: >> * None >> >> Changes since [v3]: >> * Rebased on top of linux-next top of the tree >> >> Changes since [v2]: >> * Replaced spaces with tabs in Kconfig file >> * Sorted header file inclusion alphabetically >> >> Changes since [v1]: >> * Added COMPILE_TEST in Kconfig >> * Removed empty phy_ops implementations >> * Modified code according to DT documentation file modifications >> >> drivers/phy/tegra/Kconfig | 7 ++ >> drivers/phy/tegra/Makefile | 1 + >> drivers/phy/tegra/pcie-p2u-tegra194.c | 109 ++++++++++++++++++++++++++ >> 3 files changed, 117 insertions(+) >> create mode 100644 drivers/phy/tegra/pcie-p2u-tegra194.c >> >> diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig >> index a3b1de953fb7..06d423fa85b4 100644 >> --- a/drivers/phy/tegra/Kconfig >> +++ b/drivers/phy/tegra/Kconfig >> @@ -6,3 +6,10 @@ config PHY_TEGRA_XUSB >> >> To compile this driver as a module, choose M here: the module will >> be called phy-tegra-xusb. >> + >> +config PHY_TEGRA194_PCIE_P2U >> + tristate "NVIDIA Tegra P2U PHY Driver" > > One more thing: perhaps make this description consistent with the driver > description in the source file. Done. > > Thierry >