From: sashiko-bot@kernel.org
To: "Priyank Rathod" <rathodpriyank@google.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH v5 2/2] selftests/pcie_lmr: Add tests for the Lane Margining debugfs interface
Date: Tue, 06 Oct 2026 17:40:05 +0000 [thread overview]
Message-ID: <sashiko-outbox-162301@kernel.org> (raw)
In-Reply-To: <20261006-pcie-link-endpoints-v5-2-c1e73235746b@google.com>
> Add a KTAP test for the Lane Margining at the Receiver debugfs
> interface.
>
> By default it only runs checks that do not start a margining session,
> on every pcie_lmr_* directory: the files exist, malformed input is
> rejected, and commands fail with ENOTCONN without a session.
>
> If PCIE_LMR_DEV names a port, it also starts a session on that link,
> checks the receiver and step bounds the receiver reports, and checks
> that Link Control and Link Control 2 of both ends are the same after
> the session as before it.
>
> Signed-off-by: Priyank Rathod <rathodpriyank@google.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261006-pcie-link-endpoints-v5-0-c1e73235746b@google.com?part=2
prev parent reply other threads:[~2026-10-06 17:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-06 17:34 [PATCH v5 0/2] PCI: Add Lane Margining at the Receiver debugfs interface Priyank Rathod
2026-10-06 17:34 ` [PATCH v5 1/2] PCI/LMR: " Priyank Rathod
2026-10-06 17:45 ` sashiko-bot
2026-10-06 17:34 ` [PATCH v5 2/2] selftests/pcie_lmr: Add tests for the Lane Margining " Priyank Rathod
2026-10-06 17:40 ` sashiko-bot [this message]
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