Re: [PATCH] PCI: qcom: Disable halting feature

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] pci: qcom: halt registers not cleared on 2.9.0 SoCs due to ignored flag
--

commit 209095cd3cdb28151146164ab8aa7f9f0f975948
Author: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

PCI: qcom: Disable halting feature

This commit adds a noc_ensures_ordering flag to the PCIe configuration
for SoCs where the NoC handles inbound transaction ordering. Setting this
flag disables the PARF write, read, and BDF halt features at the
controller, which aims to improve inbound DMA bandwidth. The logic to
clear these registers is added to qcom_pcie_init_2_7_0() and enabled for
several hardware configurations.

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index b58a607b713f5..73eb303919c19 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c

[ ... ]

> @@ -1624,15 +1652,18 @@ static const struct qcom_pcie_cfg cfg_2_4_0 = {
>  
>  static const struct qcom_pcie_cfg cfg_2_7_0 = {
>  	.ops = &ops_2_7_0,
> +	.noc_ensures_ordering = true,
>  };
>  
>  static const struct qcom_pcie_cfg cfg_2_9_0 = {
>  	.ops = &ops_2_9_0,
> +	.noc_ensures_ordering = true,
>  };

[Severity: Medium]
Will this flag actually take effect for 2.9.0 SoCs?

Looking at the initialization routine for 2.9.0:

drivers/pci/controller/dwc/pcie-qcom.c:qcom_pcie_init_2_9_0() {
	struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
	struct device *dev = pcie->pci->dev;
	int ret;
	...
}

It does not appear to check the noc_ensures_ordering flag or implement the
logic to clear the PARF AXI_MSTR halt registers.

Since the flag is explicitly set here to optimize performance, it seems the
inbound DMA bandwidth improvement intended by disabling the halt features will
be completely missed on 2.9.0 hardware.

Does qcom_pcie_init_2_9_0() also need to implement the halt register clearing
logic, similar to the updates made in qcom_pcie_init_2_7_0()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261009-halt-v1-1-4a2d7899d91f@oss.qualcomm.com?part=1