Re: [Patch v2 12/24] perf/x86/intel: Allocate arch-PEBS buffer and initialize PEBS_BASE MSR

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

On 2/25/2025 7:25 PM, Peter Zijlstra wrote:
> On Tue, Feb 18, 2025 at 03:28:06PM +0000, Dapeng Mi wrote:
>> Arch-PEBS introduces a new MSR IA32_PEBS_BASE to store the arch-PEBS
>> buffer physical address. This patch allocates arch-PEBS buffer and then
>> initialize IA32_PEBS_BASE MSR with the buffer physical address.
> Just to clarify, parts with ARCH PEBS will not have BTS and thus not
> have DS?

No, DS and BTS still exist along with arch-PEBS, only the legacy DS based
PEBS is unavailable and replaced by arch-PEBS.

Here is output of CPUID.1:EDX[21] and IA32_MISC_ENABLE MSR on PTL.

sudo cpuid -l 0x1 | grep DS
      DS: debug store                        = true
      DS: debug store                        = true
      DS: debug store                        = true
      DS: debug store                        = true
      DS: debug store                        = true
      DS: debug store                        = true

sudo rdmsr 0x1a0 -a
851089
851089
851089
851089
851089
851089

We can see debug store is supported, BTS_UNAVAILABLE bit (bit[11] of
IA32_MISC_ENABLE) is cleared but PEBS_UNAVAILABLE bit (bit[12] of
IA32_MISC_ENABLE) is set.