From: Xing Zhengjun <zhengjun.xing@linux.intel.com>
To: Ian Rogers <irogers@google.com>,
Kan Liang <kan.liang@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andi Kleen <ak@linux.intel.com>,
James Clark <james.clark@arm.com>,
John Garry <john.garry@huawei.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org
Cc: Stephane Eranian <eranian@google.com>
Subject: Re: [PATCH 6/8] perf vendor events: Update events for SkylakeX
Date: Fri, 18 Mar 2022 17:21:11 +0800 [thread overview]
Message-ID: <05c591ad-0f50-842e-b1b0-a93118f66240@linux.intel.com> (raw)
In-Reply-To: <20220317182858.484474-6-irogers@google.com>
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/skylakex/cache.json | 36 +++++++++++++++++++
> .../pmu-events/arch/x86/skylakex/other.json | 36 -------------------
> 2 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> index 821d2f2a8f25..6639e18a7068 100644
> --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> @@ -1686,5 +1686,41 @@
> "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
> "SampleAfterValue": "100003",
> "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json
> index 8b344259176f..779654e62d97 100644
> --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json
> +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json
> @@ -76,41 +76,5 @@
> "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
> "SampleAfterValue": "2000003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x4"
> }
> ]
> \ No newline at end of file
--
Zhengjun Xing
next prev parent reply other threads:[~2022-03-18 9:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220317182858.484474-1-irogers@google.com>
2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers
2022-03-18 9:12 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers
2022-03-18 9:15 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers
2022-03-18 9:19 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers
2022-03-18 9:19 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers
2022-03-18 9:21 ` Xing Zhengjun [this message]
2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers
2022-03-18 9:22 ` Xing Zhengjun
2022-03-18 9:14 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX John Garry
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