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X-CSE-ConnectionGUID: oa3/YYaKQO6odQSdazniyQ== X-CSE-MsgGUID: 3GztiEFjQDSzIpEuObfM3A== X-IronPort-AV: E=McAfee;i="6700,10204,11235"; a="54887261" X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="54887261" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 19:50:41 -0700 X-CSE-ConnectionGUID: vNMJ1xhxSkWl7JrckhB5pQ== X-CSE-MsgGUID: cKkij09BTw6pfRCIL3O3mA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,231,1725346800"; d="scan'208";a="81214460" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.125.240.3]) ([10.125.240.3]) by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2024 19:50:35 -0700 Message-ID: <05ef9830-0a76-4e15-a084-f614c5a85a00@linux.intel.com> Date: Fri, 25 Oct 2024 10:50:33 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 27/58] KVM: x86/pmu: Create a function prototype to disable MSR interception To: "Chen, Zide" , Mingwei Zhang , Sean Christopherson , Paolo Bonzini , Xiong Zhang , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das Cc: Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org References: <20240801045907.4010984-1-mizhang@google.com> <20240801045907.4010984-28-mizhang@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/25/2024 3:58 AM, Chen, Zide wrote: > > On 7/31/2024 9:58 PM, Mingwei Zhang wrote: >> Add one extra pmu function prototype in kvm_pmu_ops to disable PMU MSR >> interception. >> >> Signed-off-by: Mingwei Zhang >> Signed-off-by: Dapeng Mi >> Tested-by: Yongwei Ma >> --- >> arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 + >> arch/x86/kvm/cpuid.c | 4 ++++ >> arch/x86/kvm/pmu.c | 5 +++++ >> arch/x86/kvm/pmu.h | 2 ++ >> 4 files changed, 12 insertions(+) >> >> diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h >> index fd986d5146e4..1b7876dcb3c3 100644 >> --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h >> +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h >> @@ -24,6 +24,7 @@ KVM_X86_PMU_OP(is_rdpmc_passthru_allowed) >> KVM_X86_PMU_OP_OPTIONAL(reset) >> KVM_X86_PMU_OP_OPTIONAL(deliver_pmi) >> KVM_X86_PMU_OP_OPTIONAL(cleanup) >> +KVM_X86_PMU_OP_OPTIONAL(passthrough_pmu_msrs) >> >> #undef KVM_X86_PMU_OP >> #undef KVM_X86_PMU_OP_OPTIONAL >> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c >> index f2f2be5d1141..3deb79b39847 100644 >> --- a/arch/x86/kvm/cpuid.c >> +++ b/arch/x86/kvm/cpuid.c >> @@ -381,6 +381,10 @@ static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) >> vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); >> >> kvm_pmu_refresh(vcpu); >> + >> + if (is_passthrough_pmu_enabled(vcpu)) >> + kvm_pmu_passthrough_pmu_msrs(vcpu); >> + >> vcpu->arch.cr4_guest_rsvd_bits = >> __cr4_reserved_bits(guest_cpuid_has, vcpu); >> >> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c >> index 3afefe4cf6e2..bd94f2d67f5c 100644 >> --- a/arch/x86/kvm/pmu.c >> +++ b/arch/x86/kvm/pmu.c >> @@ -1059,3 +1059,8 @@ int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp) >> kfree(filter); >> return r; >> } >> + >> +void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) >> +{ >> + static_call_cond(kvm_x86_pmu_passthrough_pmu_msrs)(vcpu); >> +} >> diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h >> index e1af6d07b191..63f876557716 100644 >> --- a/arch/x86/kvm/pmu.h >> +++ b/arch/x86/kvm/pmu.h >> @@ -41,6 +41,7 @@ struct kvm_pmu_ops { >> void (*deliver_pmi)(struct kvm_vcpu *vcpu); >> void (*cleanup)(struct kvm_vcpu *vcpu); >> bool (*is_rdpmc_passthru_allowed)(struct kvm_vcpu *vcpu); >> + void (*passthrough_pmu_msrs)(struct kvm_vcpu *vcpu); > Seems after_set_cpuid() is a better name. It's more generic to reflect > the fact that PMU needs to do something after userspace sets CPUID. > Currently PMU needs to update the MSR interception policy, but it may > want to do more in the future. > > Also, it's more consistent to other APIs called in > kvm_vcpu_after_set_cpuid(). Looks reasonable. > >> >> const u64 EVENTSEL_EVENT; >> const int MAX_NR_GP_COUNTERS; >> @@ -292,6 +293,7 @@ void kvm_pmu_destroy(struct kvm_vcpu *vcpu); >> int kvm_vm_ioctl_set_pmu_event_filter(struct kvm *kvm, void __user *argp); >> void kvm_pmu_trigger_event(struct kvm_vcpu *vcpu, u64 eventsel); >> bool kvm_pmu_check_rdpmc_passthrough(struct kvm_vcpu *vcpu); >> +void kvm_pmu_passthrough_pmu_msrs(struct kvm_vcpu *vcpu); >> >> bool is_vmware_backdoor_pmc(u32 pmc_idx); >>