* [PATCH 2/8] perf vendor events: Update events for Elkhartlake
[not found] <20220317182858.484474-1-irogers@google.com>
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:12 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers
` (5 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the pipeline topic. Update the
perf json files for this change.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../arch/x86/elkhartlake/other.json | 241 ------------------
.../arch/x86/elkhartlake/pipeline.json | 241 ++++++++++++++++++
2 files changed, 241 insertions(+), 241 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
index 627691404155..de55b199ba79 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
@@ -179,246 +179,5 @@
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
- "SampleAfterValue": "1000003",
- "UMask": "0x6"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
- "Counter": "0,1,2,3",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
- "Counter": "0,1,2,3",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x73",
- "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.REGISTER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x20"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x40"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x10"
- },
- {
- "BriefDescription": "This event is deprecated.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x74",
- "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.ALL",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
- "SampleAfterValue": "1000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
- "SampleAfterValue": "1000003",
- "UMask": "0x40"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.CISC",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.DECODE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.ITLB",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
- "SampleAfterValue": "1000003",
- "UMask": "0x10"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.OTHER",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x80"
- },
- {
- "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x71",
- "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
- "PDIR_COUNTER": "na",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "Counts the total number of consumed retirement slots.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xc2",
- "EventName": "TOPDOWN_RETIRING.ALL",
- "PEBS": "1",
- "PEBScounters": "0,1,2,3",
- "SampleAfterValue": "1000003"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
index 41e5dfad8f51..31816c6543a8 100644
--- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
@@ -262,6 +262,247 @@
"PEBScounters": "0,1,2,3",
"SampleAfterValue": "20003"
},
+ {
+ "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x6"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x73",
+ "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.ALL",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.REGISTER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x20"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x40"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "This event is deprecated.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x74",
+ "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.ALL",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x40"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.CISC",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.DECODE",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.ITLB",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.OTHER",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x80"
+ },
+ {
+ "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x71",
+ "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
+ "PDIR_COUNTER": "na",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Counts the total number of consumed retirement slots.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xc2",
+ "EventName": "TOPDOWN_RETIRING.ALL",
+ "PEBS": "1",
+ "PEBScounters": "0,1,2,3",
+ "SampleAfterValue": "1000003"
+ },
{
"BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
"CollectPEBSRecord": "2",
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/8] perf vendor events: Update events for Elkhartlake
2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers
@ 2022-03-18 9:12 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:12 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the pipeline topic. Update the
> perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../arch/x86/elkhartlake/other.json | 241 ------------------
> .../arch/x86/elkhartlake/pipeline.json | 241 ++++++++++++++++++
> 2 files changed, 241 insertions(+), 241 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> index 627691404155..de55b199ba79 100644
> --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json
> @@ -179,246 +179,5 @@
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x73",
> - "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x6"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x73",
> - "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x73",
> - "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x73",
> - "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x73",
> - "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.ALL",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.REGISTER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x20"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x40"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x10"
> - },
> - {
> - "BriefDescription": "This event is deprecated.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x74",
> - "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.ALL",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x40"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.CISC",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.DECODE",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.ITLB",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x10"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.OTHER",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x80"
> - },
> - {
> - "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x71",
> - "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
> - "PDIR_COUNTER": "na",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "Counts the total number of consumed retirement slots.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xc2",
> - "EventName": "TOPDOWN_RETIRING.ALL",
> - "PEBS": "1",
> - "PEBScounters": "0,1,2,3",
> - "SampleAfterValue": "1000003"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> index 41e5dfad8f51..31816c6543a8 100644
> --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json
> @@ -262,6 +262,247 @@
> "PEBScounters": "0,1,2,3",
> "SampleAfterValue": "20003"
> },
> + {
> + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x6"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "This event is deprecated. Refer to new event TOPDOWN_BAD_SPECULATION.FASTNUKE",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x73",
> + "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.REGISTER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x20"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x40"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "This event is deprecated.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x74",
> + "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to frontend stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.ALL",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x40"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.CISC",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.DECODE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.ITLB",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.OTHER",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x80"
> + },
> + {
> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x71",
> + "EventName": "TOPDOWN_FE_BOUND.PREDECODE",
> + "PDIR_COUNTER": "na",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Counts the total number of consumed retirement slots.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xc2",
> + "EventName": "TOPDOWN_RETIRING.ALL",
> + "PEBS": "1",
> + "PEBScounters": "0,1,2,3",
> + "SampleAfterValue": "1000003"
> + },
> {
> "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).",
> "CollectPEBSRecord": "2",
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/8] perf vendor events: Update events for Icelake
[not found] <20220317182858.484474-1-irogers@google.com>
2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:15 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers
` (4 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache and pipeline topic.
Update the perf json files for this change.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelake/cache.json | 633 +++++++++++++++
.../pmu-events/arch/x86/icelake/other.json | 752 +-----------------
.../pmu-events/arch/x86/icelake/pipeline.json | 47 ++
3 files changed, 716 insertions(+), 716 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json
index 96dcd387c70e..375ce490833c 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
@@ -553,6 +553,591 @@
"SampleAfterValue": "50021",
"UMask": "0x20"
},
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C0004",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0400",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0400",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0400",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C0010",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C0020",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C2380",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C8000",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x2003C8000",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1003C8000",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1E003C8000",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3FC03C0800",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Demand and prefetch data reads",
"CollectPEBSRecord": "2",
@@ -674,5 +1259,53 @@
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json
index 10e8582774ce..08f6321025e8 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/other.json
@@ -78,418 +78,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C0004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000004",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000400",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
+ "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0400",
+ "MSRValue": "0x184000004",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -498,13 +93,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "BriefDescription": "Counts demand data reads that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
+ "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0400",
+ "MSRValue": "0x10001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -513,13 +108,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
+ "EventName": "OCR.DEMAND_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0400",
+ "MSRValue": "0x184000001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -528,13 +123,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
+ "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
+ "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000400",
+ "MSRValue": "0x184000001",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -543,13 +138,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
+ "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10010",
+ "MSRValue": "0x10002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -558,13 +153,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
+ "EventName": "OCR.DEMAND_RFO.DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x184000010",
+ "MSRValue": "0x184000002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -573,13 +168,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
+ "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0010",
+ "MSRValue": "0x184000002",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -588,13 +183,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0010",
+ "MSRValue": "0x10400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -603,13 +198,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0010",
+ "MSRValue": "0x184000400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -618,13 +213,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0010",
+ "MSRValue": "0x184000400",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -633,13 +228,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
+ "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0010",
+ "MSRValue": "0x10010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -648,13 +243,13 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
+ "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
+ "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C0010",
+ "MSRValue": "0x184000010",
"Offcore": "1",
"PEBScounters": "0,1,2,3",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
@@ -707,96 +302,6 @@
"Speculative": "1",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C0020",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
"CollectPEBSRecord": "2",
@@ -812,21 +317,6 @@
"Speculative": "1",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C2380",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
"CollectPEBSRecord": "2",
@@ -857,66 +347,6 @@
"Speculative": "1",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x2003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x1E003C8000",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
"CollectPEBSRecord": "2",
@@ -962,21 +392,6 @@
"Speculative": "1",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3FC03C0800",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
"CollectPEBSRecord": "2",
@@ -991,100 +406,5 @@
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
- "EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
- "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x1"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
index 2b305bdc8cfc..573ac7ac8879 100644
--- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
@@ -730,6 +730,53 @@
"Speculative": "1",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "Fixed counter 3",
+ "EventName": "TOPDOWN.SLOTS",
+ "PEBScounters": "35",
+ "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.SLOTS_P",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
"CollectPEBSRecord": "2",
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 3/8] perf vendor events: Update events for Icelake
2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers
@ 2022-03-18 9:15 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:15 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache and pipeline topic.
> Update the perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/icelake/cache.json | 633 +++++++++++++++
> .../pmu-events/arch/x86/icelake/other.json | 752 +-----------------
> .../pmu-events/arch/x86/icelake/pipeline.json | 47 ++
> 3 files changed, 716 insertions(+), 716 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf/pmu-events/arch/x86/icelake/cache.json
> index 96dcd387c70e..375ce490833c 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json
> @@ -553,6 +553,591 @@
> "SampleAfterValue": "50021",
> "UMask": "0x20"
> },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C0004",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0400",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0400",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0400",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C0010",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C0020",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C2380",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C8000",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x2003C8000",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1003C8000",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1E003C8000",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3FC03C0800",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Demand and prefetch data reads",
> "CollectPEBSRecord": "2",
> @@ -674,5 +1259,53 @@
> "SampleAfterValue": "100003",
> "Speculative": "1",
> "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf/pmu-events/arch/x86/icelake/other.json
> index 10e8582774ce..08f6321025e8 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json
> @@ -78,418 +78,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a cacheline in the L3 where a snoop was sent.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C0004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000004",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that have any type of response.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop was sent.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop was sent.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10400",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000400",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY",
> + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0400",
> + "MSRValue": "0x184000004",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -498,13 +93,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "BriefDescription": "Counts demand data reads that have any type of response.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS",
> + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0400",
> + "MSRValue": "0x10001",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -513,13 +108,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED",
> + "EventName": "OCR.DEMAND_DATA_RD.DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0400",
> + "MSRValue": "0x184000001",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -528,13 +123,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
> + "BriefDescription": "Counts demand data reads that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
> + "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000400",
> + "MSRValue": "0x184000001",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -543,13 +138,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
> + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10010",
> + "MSRValue": "0x10002",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -558,13 +153,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
> + "EventName": "OCR.DEMAND_RFO.DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x184000010",
> + "MSRValue": "0x184000002",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -573,13 +168,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY",
> + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0010",
> + "MSRValue": "0x184000002",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -588,13 +183,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0010",
> + "MSRValue": "0x10400",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -603,13 +198,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0010",
> + "MSRValue": "0x184000400",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -618,13 +213,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0010",
> + "MSRValue": "0x184000400",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -633,13 +228,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
> + "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0010",
> + "MSRValue": "0x10010",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -648,13 +243,13 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
> + "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT",
> + "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C0010",
> + "MSRValue": "0x184000010",
> "Offcore": "1",
> "PEBScounters": "0,1,2,3",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> @@ -707,96 +302,6 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that hit a cacheline in the L3 where a snoop was sent.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C0020",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> @@ -812,21 +317,6 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts hardware prefetches to the L3 only that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L3.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C2380",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
> "CollectPEBSRecord": "2",
> @@ -857,66 +347,6 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in another core, data forwarding is not required.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C8000",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent but no other cores had the data.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x2003C8000",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was not needed to satisfy the request.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1003C8000",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that hit a cacheline in the L3 where a snoop was sent.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x1E003C8000",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> @@ -962,21 +392,6 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts streaming stores that hit a cacheline in the L3 where a snoop was sent or not.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.STREAMING_WR.L3_HIT.ANY",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3FC03C0800",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts streaming stores that DRAM supplied the request.",
> "CollectPEBSRecord": "2",
> @@ -991,100 +406,5 @@
> "SampleAfterValue": "100003",
> "Speculative": "1",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "Fixed counter 3",
> - "EventName": "TOPDOWN.SLOTS",
> - "PEBScounters": "35",
> - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.SLOTS_P",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x1"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> index 2b305bdc8cfc..573ac7ac8879 100644
> --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json
> @@ -730,6 +730,53 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "Fixed counter 3",
> + "EventName": "TOPDOWN.SLOTS",
> + "PEBScounters": "35",
> + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.SLOTS_P",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
> "CollectPEBSRecord": "2",
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 4/8] perf vendor events: Update events for IcelakeX
[not found] <20220317182858.484474-1-irogers@google.com>
2022-03-17 18:28 ` [PATCH 2/8] perf vendor events: Update events for Elkhartlake Ian Rogers
2022-03-17 18:28 ` [PATCH 3/8] perf vendor events: Update events for Icelake Ian Rogers
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:19 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers
` (3 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
Move from v1.11 to v1.12.
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache, memory and
pipeline topics. Update the perf json files for this change.
Tested:
```
...
6: Parse event definition strings : Ok
...
91: perf all PMU test : Ok
...
```
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/icelakex/cache.json | 252 +++++++++++++++
.../pmu-events/arch/x86/icelakex/memory.json | 26 +-
.../pmu-events/arch/x86/icelakex/other.json | 287 ++----------------
.../arch/x86/icelakex/pipeline.json | 35 +++
4 files changed, 324 insertions(+), 276 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
index 104409fd8647..3c4da0371df9 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
@@ -657,6 +657,30 @@
"SampleAfterValue": "100003",
"UMask": "0x80"
},
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0004",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3",
@@ -681,6 +705,54 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0001",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
"Counter": "0,1,2,3",
@@ -729,6 +801,30 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0002",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
"Counter": "0,1,2,3",
@@ -753,6 +849,102 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C0400",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.HWPF_L3.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80082380",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.PREFETCHES.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F803C27F0",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x3F003C0477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x4003C0477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x1830000477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
"Counter": "0,1,2,3",
@@ -801,6 +993,18 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.STREAMING_WR.L3_HIT",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x80080800",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Demand and prefetch data reads",
"CollectPEBSRecord": "2",
@@ -947,5 +1151,53 @@
"SampleAfterValue": "100003",
"Speculative": "1",
"UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "SampleAfterValue": "100003",
+ "Speculative": "1",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
index 9ebcd442e6d3..c10a1bbc66b1 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
@@ -169,7 +169,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F8CC00004",
+ "MSRValue": "0x3F84400004",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -193,7 +193,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F8CC00001",
+ "MSRValue": "0x3F84400001",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -217,7 +217,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F0CC00002",
+ "MSRValue": "0x3F04400002",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -241,7 +241,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F8CC00400",
+ "MSRValue": "0x3F84400400",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -301,7 +301,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.OTHER.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F8CC08000",
+ "MSRValue": "0x3F84408000",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -313,7 +313,7 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F8CC027F0",
+ "MSRValue": "0x3F844027F0",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -337,7 +337,19 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F0CC00477",
+ "MSRValue": "0x3F04400477",
+ "Offcore": "1",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x70CC00477",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
index 43524f274307..1246b22769da 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
@@ -156,31 +156,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0004",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that the DRAM attached to this socket supplied the request.",
+ "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
@@ -228,55 +204,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0001",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand data reads that the DRAM attached to this socket supplied the request.",
+ "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
@@ -288,7 +216,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket.",
+ "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
@@ -384,31 +312,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that the DRAM attached to this socket supplied the request.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
@@ -420,7 +324,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket.",
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
@@ -492,19 +396,7 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C0400",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that the DRAM attached to this socket supplied the request.",
+ "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
@@ -527,18 +419,6 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.HWPF_L3.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80082380",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
"Counter": "0,1,2,3",
@@ -575,18 +455,6 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
- {
- "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.PREFETCHES.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F803C27F0",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
"Counter": "0,1,2,3",
@@ -612,72 +480,48 @@
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x3F003C0477",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0477",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
+ "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x4003C0477",
+ "MSRValue": "0x104000477",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0477",
+ "MSRValue": "0x100400477",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that the DRAM attached to this socket supplied the request.",
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
+ "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x104000477",
+ "MSRValue": "0x70C000477",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
- "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket.",
+ "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
"Counter": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
- "EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
+ "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
"MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x100400477",
+ "MSRValue": "0x700C00477",
"Offcore": "1",
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
@@ -754,100 +598,5 @@
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.STREAMING_WR.L3_HIT",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x80080800",
- "Offcore": "1",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "SampleAfterValue": "100003",
- "Speculative": "1",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
- "EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
- "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
- "SampleAfterValue": "10000003",
- "Speculative": "1",
- "UMask": "0x1"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
index 9a0b4907cb3a..068a3d46b443 100644
--- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
@@ -728,6 +728,41 @@
"Speculative": "1",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "Fixed counter 3",
+ "EventName": "TOPDOWN.SLOTS",
+ "PEBScounters": "35",
+ "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.SLOTS_P",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
+ "SampleAfterValue": "10000003",
+ "Speculative": "1",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
"CollectPEBSRecord": "2",
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 4/8] perf vendor events: Update events for IcelakeX
2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers
@ 2022-03-18 9:19 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:19 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> Move from v1.11 to v1.12.
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache, memory and
> pipeline topics. Update the perf json files for this change.
>
> Tested:
> ```
> ...
> 6: Parse event definition strings : Ok
> ...
> 91: perf all PMU test : Ok
> ...
> ```
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/icelakex/cache.json | 252 +++++++++++++++
> .../pmu-events/arch/x86/icelakex/memory.json | 26 +-
> .../pmu-events/arch/x86/icelakex/other.json | 287 ++----------------
> .../arch/x86/icelakex/pipeline.json | 35 +++
> 4 files changed, 324 insertions(+), 276 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
> index 104409fd8647..3c4da0371df9 100644
> --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json
> @@ -657,6 +657,30 @@
> "SampleAfterValue": "100003",
> "UMask": "0x80"
> },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F803C0004",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0004",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
> "Counter": "0,1,2,3",
> @@ -681,6 +705,54 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F803C0001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x8003C0001",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
> "Counter": "0,1,2,3",
> @@ -729,6 +801,30 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F803C0002",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0002",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
> "Counter": "0,1,2,3",
> @@ -753,6 +849,102 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F803C0400",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.HWPF_L3.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x80082380",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.PREFETCHES.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F803C27F0",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x3F003C0477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x4003C0477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x8003C0477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x1830000477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
> "Counter": "0,1,2,3",
> @@ -801,6 +993,18 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.STREAMING_WR.L3_HIT",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x80080800",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Demand and prefetch data reads",
> "CollectPEBSRecord": "2",
> @@ -947,5 +1151,53 @@
> "SampleAfterValue": "100003",
> "Speculative": "1",
> "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "SampleAfterValue": "100003",
> + "Speculative": "1",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
> index 9ebcd442e6d3..c10a1bbc66b1 100644
> --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json
> +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json
> @@ -169,7 +169,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F8CC00004",
> + "MSRValue": "0x3F84400004",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -193,7 +193,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F8CC00001",
> + "MSRValue": "0x3F84400001",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -217,7 +217,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F0CC00002",
> + "MSRValue": "0x3F04400002",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -241,7 +241,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F8CC00400",
> + "MSRValue": "0x3F84400400",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -301,7 +301,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.OTHER.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F8CC08000",
> + "MSRValue": "0x3F84408000",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -313,7 +313,7 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F8CC027F0",
> + "MSRValue": "0x3F844027F0",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -337,7 +337,19 @@
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F0CC00477",
> + "MSRValue": "0x3F04400477",
> + "Offcore": "1",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that missed the L3 Cache and were supplied by the local socket (DRAM or PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM or DRAM accesses that are controlled by the close or distant SNC Cluster.",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x70CC00477",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/perf/pmu-events/arch/x86/icelakex/other.json
> index 43524f274307..1246b22769da 100644
> --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json
> +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json
> @@ -156,31 +156,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F803C0004",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0004",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that the DRAM attached to this socket supplied the request.",
> + "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
> @@ -228,55 +204,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F803C0001",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0001",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0001",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x8003C0001",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand data reads that the DRAM attached to this socket supplied the request.",
> + "BriefDescription": "Counts demand data reads that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
> @@ -288,7 +216,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket.",
> + "BriefDescription": "Counts demand data reads that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM",
> @@ -384,31 +312,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F803C0002",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0002",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that the DRAM attached to this socket supplied the request.",
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
> @@ -420,7 +324,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket.",
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.DEMAND_RFO.LOCAL_PMM",
> @@ -492,19 +396,7 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F803C0400",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that the DRAM attached to this socket supplied the request.",
> + "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
> @@ -527,18 +419,6 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.HWPF_L3.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x80082380",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts hardware prefetches to the L3 only that were not supplied by the local socket's L1, L2, or L3 caches and the cacheline was homed in a remote socket.",
> "Counter": "0,1,2,3",
> @@ -575,18 +455,6 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> - {
> - "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.PREFETCHES.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F803C27F0",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that have any type of response.",
> "Counter": "0,1,2,3",
> @@ -612,72 +480,48 @@
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x3F003C0477",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0477",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
> + "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x4003C0477",
> + "MSRValue": "0x104000477",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those PMM accesses that are controlled by the close SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
> + "EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x8003C0477",
> + "MSRValue": "0x100400477",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that the DRAM attached to this socket supplied the request.",
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are controlled by the close or distant SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
> + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x104000477",
> + "MSRValue": "0x70C000477",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> {
> - "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket.",
> + "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are controlled by the close or distant SNC Cluster.",
> "Counter": "0,1,2,3",
> "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.READS_TO_CORE.LOCAL_PMM",
> + "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM",
> "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x100400477",
> + "MSRValue": "0x700C00477",
> "Offcore": "1",
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> @@ -754,100 +598,5 @@
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.STREAMING_WR.L3_HIT",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x80080800",
> - "Offcore": "1",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "SampleAfterValue": "100003",
> - "Speculative": "1",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "Fixed counter 3",
> - "EventName": "TOPDOWN.SLOTS",
> - "PEBScounters": "35",
> - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.SLOTS_P",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> - "SampleAfterValue": "10000003",
> - "Speculative": "1",
> - "UMask": "0x1"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
> index 9a0b4907cb3a..068a3d46b443 100644
> --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json
> @@ -728,6 +728,41 @@
> "Speculative": "1",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "Fixed counter 3",
> + "EventName": "TOPDOWN.SLOTS",
> + "PEBScounters": "35",
> + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.SLOTS_P",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> + "SampleAfterValue": "10000003",
> + "Speculative": "1",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
> "CollectPEBSRecord": "2",
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 5/8] perf vendor events: Update events for Skylake
[not found] <20220317182858.484474-1-irogers@google.com>
` (2 preceding siblings ...)
2022-03-17 18:28 ` [PATCH 4/8] perf vendor events: Update events for IcelakeX Ian Rogers
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:19 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers
` (2 subsequent siblings)
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache topic. Update the
perf json files for this change.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++
.../pmu-events/arch/x86/skylake/other.json | 36 -------------------
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
index 529c5e6e117f..c5d9a4ed10d7 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
@@ -2937,5 +2937,41 @@
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
index 5c0e81f76a5b..4f4839024915 100644
--- a/tools/perf/pmu-events/arch/x86/skylake/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
@@ -16,41 +16,5 @@
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "SampleAfterValue": "2000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "SampleAfterValue": "2000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "SampleAfterValue": "2000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "SampleAfterValue": "2000003",
- "UMask": "0x4"
}
]
\ No newline at end of file
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 5/8] perf vendor events: Update events for Skylake
2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers
@ 2022-03-18 9:19 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:19 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/skylake/cache.json | 36 +++++++++++++++++++
> .../pmu-events/arch/x86/skylake/other.json | 36 -------------------
> 2 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> index 529c5e6e117f..c5d9a4ed10d7 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json
> @@ -2937,5 +2937,41 @@
> "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
> "SampleAfterValue": "100003",
> "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf/pmu-events/arch/x86/skylake/other.json
> index 5c0e81f76a5b..4f4839024915 100644
> --- a/tools/perf/pmu-events/arch/x86/skylake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json
> @@ -16,41 +16,5 @@
> "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
> "SampleAfterValue": "2000003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x4"
> }
> ]
> \ No newline at end of file
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/8] perf vendor events: Update events for SkylakeX
[not found] <20220317182858.484474-1-irogers@google.com>
` (3 preceding siblings ...)
2022-03-17 18:28 ` [PATCH 5/8] perf vendor events: Update events for Skylake Ian Rogers
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:21 ` Xing Zhengjun
2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers
2022-03-18 9:14 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX John Garry
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache topic. Update the
perf json files for this change.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/skylakex/cache.json | 36 +++++++++++++++++++
.../pmu-events/arch/x86/skylakex/other.json | 36 -------------------
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
index 821d2f2a8f25..6639e18a7068 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
@@ -1686,5 +1686,41 @@
"PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x10"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "Counter": "0,1,2,3",
+ "CounterHTOff": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json
index 8b344259176f..779654e62d97 100644
--- a/tools/perf/pmu-events/arch/x86/skylakex/other.json
+++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json
@@ -76,41 +76,5 @@
"EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
"SampleAfterValue": "2000003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "SampleAfterValue": "2000003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "SampleAfterValue": "2000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "SampleAfterValue": "2000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "Counter": "0,1,2,3",
- "CounterHTOff": "0,1,2,3,4,5,6,7",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "SampleAfterValue": "2000003",
- "UMask": "0x4"
}
]
\ No newline at end of file
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 6/8] perf vendor events: Update events for SkylakeX
2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers
@ 2022-03-18 9:21 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:21 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/skylakex/cache.json | 36 +++++++++++++++++++
> .../pmu-events/arch/x86/skylakex/other.json | 36 -------------------
> 2 files changed, 36 insertions(+), 36 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> index 821d2f2a8f25..6639e18a7068 100644
> --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json
> @@ -1686,5 +1686,41 @@
> "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
> "SampleAfterValue": "100003",
> "UMask": "0x10"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "Counter": "0,1,2,3",
> + "CounterHTOff": "0,1,2,3,4,5,6,7",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "SampleAfterValue": "2000003",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/perf/pmu-events/arch/x86/skylakex/other.json
> index 8b344259176f..779654e62d97 100644
> --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json
> +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json
> @@ -76,41 +76,5 @@
> "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET",
> "SampleAfterValue": "2000003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "Counter": "0,1,2,3",
> - "CounterHTOff": "0,1,2,3,4,5,6,7",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "SampleAfterValue": "2000003",
> - "UMask": "0x4"
> }
> ]
> \ No newline at end of file
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 7/8] perf vendor events: Update events for Tigerlake
[not found] <20220317182858.484474-1-irogers@google.com>
` (4 preceding siblings ...)
2022-03-17 18:28 ` [PATCH 6/8] perf vendor events: Update events for SkylakeX Ian Rogers
@ 2022-03-17 18:28 ` Ian Rogers
2022-03-18 9:22 ` Xing Zhengjun
2022-03-18 9:14 ` [PATCH 1/8] perf vendor events: Update events for CascadelakeX John Garry
6 siblings, 1 reply; 13+ messages in thread
From: Ian Rogers @ 2022-03-17 18:28 UTC (permalink / raw)
To: Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian, Ian Rogers
The change:
https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
moved certain "other" type of events in to the cache and pipeline topics.
Update the perf json files for this change.
Signed-off-by: Ian Rogers <irogers@google.com>
---
.../pmu-events/arch/x86/tigerlake/cache.json | 86 ++++++++++++
.../pmu-events/arch/x86/tigerlake/other.json | 129 ------------------
.../arch/x86/tigerlake/pipeline.json | 43 ++++++
3 files changed, 129 insertions(+), 129 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
index 543a3298f86f..0569b2c704ca 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
@@ -493,6 +493,48 @@
"SampleAfterValue": "50021",
"UMask": "0x20"
},
+ {
+ "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x8003C0001",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB7, 0xBB",
+ "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "MSRValue": "0x10003C0002",
+ "Offcore": "1",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Demand and prefetch data reads",
"CollectPEBSRecord": "2",
@@ -627,5 +669,49 @@
"PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
"SampleAfterValue": "100003",
"UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHNTA instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.NTA",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHW instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT0 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T0",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x32",
+ "EventName": "SW_PREFETCH_ACCESS.T1_T2",
+ "PEBScounters": "0,1,2,3",
+ "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
+ "SampleAfterValue": "100003",
+ "UMask": "0x4"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
index b1143fe74246..304cd09fe159 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
@@ -43,48 +43,6 @@
"SampleAfterValue": "200003",
"UMask": "0x20"
},
- {
- "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x8003C0001",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0xB7, 0xBB",
- "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
- "MSRIndex": "0x1a6,0x1a7",
- "MSRValue": "0x10003C0002",
- "Offcore": "1",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
{
"BriefDescription": "Counts streaming stores that have any type of response.",
"CollectPEBSRecord": "2",
@@ -98,92 +56,5 @@
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"SampleAfterValue": "100003",
"UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHNTA instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.NTA",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
- "SampleAfterValue": "100003",
- "UMask": "0x1"
- },
- {
- "BriefDescription": "Number of PREFETCHW instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
- "SampleAfterValue": "100003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "Number of PREFETCHT0 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T0",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
- "SampleAfterValue": "100003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3",
- "EventCode": "0x32",
- "EventName": "SW_PREFETCH_ACCESS.T1_T2",
- "PEBScounters": "0,1,2,3",
- "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
- "SampleAfterValue": "100003",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
- "SampleAfterValue": "10000003",
- "UMask": "0x2"
- },
- {
- "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
- "SampleAfterValue": "10000003",
- "UMask": "0x8"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "Fixed counter 3",
- "EventName": "TOPDOWN.SLOTS",
- "PEBScounters": "35",
- "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
- "SampleAfterValue": "10000003",
- "UMask": "0x4"
- },
- {
- "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
- "CollectPEBSRecord": "2",
- "Counter": "0,1,2,3,4,5,6,7",
- "EventCode": "0xa4",
- "EventName": "TOPDOWN.SLOTS_P",
- "PEBScounters": "0,1,2,3,4,5,6,7",
- "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
- "SampleAfterValue": "10000003",
- "UMask": "0x1"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
index 4dc3a16e3da4..d436775c80db 100644
--- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
@@ -711,6 +711,49 @@
"SampleAfterValue": "100003",
"UMask": "0x1"
},
+ {
+ "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
+ "SampleAfterValue": "10000003",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
+ "SampleAfterValue": "10000003",
+ "UMask": "0x8"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "Fixed counter 3",
+ "EventName": "TOPDOWN.SLOTS",
+ "PEBScounters": "35",
+ "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
+ "SampleAfterValue": "10000003",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
+ "CollectPEBSRecord": "2",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xa4",
+ "EventName": "TOPDOWN.SLOTS_P",
+ "PEBScounters": "0,1,2,3,4,5,6,7",
+ "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
+ "SampleAfterValue": "10000003",
+ "UMask": "0x1"
+ },
{
"BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
"CollectPEBSRecord": "2",
--
2.35.1.894.gb6a874cedc-goog
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 7/8] perf vendor events: Update events for Tigerlake
2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers
@ 2022-03-18 9:22 ` Xing Zhengjun
0 siblings, 0 replies; 13+ messages in thread
From: Xing Zhengjun @ 2022-03-18 9:22 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, John Garry, linux-kernel,
linux-perf-users
Cc: Stephane Eranian
On 3/18/2022 2:28 AM, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache and pipeline topics.
> Update the perf json files for this change.
>
> Signed-off-by: Ian Rogers <irogers@google.com>
Reviewed-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
> ---
> .../pmu-events/arch/x86/tigerlake/cache.json | 86 ++++++++++++
> .../pmu-events/arch/x86/tigerlake/other.json | 129 ------------------
> .../arch/x86/tigerlake/pipeline.json | 43 ++++++
> 3 files changed, 129 insertions(+), 129 deletions(-)
>
> diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
> index 543a3298f86f..0569b2c704ca 100644
> --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
> +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json
> @@ -493,6 +493,48 @@
> "SampleAfterValue": "50021",
> "UMask": "0x20"
> },
> + {
> + "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x8003C0001",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0xB7, 0xBB",
> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> + "MSRIndex": "0x1a6,0x1a7",
> + "MSRValue": "0x10003C0002",
> + "Offcore": "1",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Demand and prefetch data reads",
> "CollectPEBSRecord": "2",
> @@ -627,5 +669,49 @@
> "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
> "SampleAfterValue": "100003",
> "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.NTA",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x1"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHW instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T0",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3",
> + "EventCode": "0x32",
> + "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> + "PEBScounters": "0,1,2,3",
> + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> + "SampleAfterValue": "100003",
> + "UMask": "0x4"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
> index b1143fe74246..304cd09fe159 100644
> --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json
> +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json
> @@ -43,48 +43,6 @@
> "SampleAfterValue": "200003",
> "UMask": "0x20"
> },
> - {
> - "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x8003C0001",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0xB7, 0xBB",
> - "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
> - "MSRIndex": "0x1a6,0x1a7",
> - "MSRValue": "0x10003C0002",
> - "Offcore": "1",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> {
> "BriefDescription": "Counts streaming stores that have any type of response.",
> "CollectPEBSRecord": "2",
> @@ -98,92 +56,5 @@
> "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHNTA instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.NTA",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x1"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHW instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT0 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T0",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3",
> - "EventCode": "0x32",
> - "EventName": "SW_PREFETCH_ACCESS.T1_T2",
> - "PEBScounters": "0,1,2,3",
> - "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
> - "SampleAfterValue": "100003",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> - "SampleAfterValue": "10000003",
> - "UMask": "0x2"
> - },
> - {
> - "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
> - "SampleAfterValue": "10000003",
> - "UMask": "0x8"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "Fixed counter 3",
> - "EventName": "TOPDOWN.SLOTS",
> - "PEBScounters": "35",
> - "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> - "SampleAfterValue": "10000003",
> - "UMask": "0x4"
> - },
> - {
> - "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> - "CollectPEBSRecord": "2",
> - "Counter": "0,1,2,3,4,5,6,7",
> - "EventCode": "0xa4",
> - "EventName": "TOPDOWN.SLOTS_P",
> - "PEBScounters": "0,1,2,3,4,5,6,7",
> - "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> - "SampleAfterValue": "10000003",
> - "UMask": "0x1"
> }
> ]
> \ No newline at end of file
> diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
> index 4dc3a16e3da4..d436775c80db 100644
> --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
> +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json
> @@ -711,6 +711,49 @@
> "SampleAfterValue": "100003",
> "UMask": "0x1"
> },
> + {
> + "BriefDescription": "TMA slots where no uops were being issued due to lack of back-end resources.",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of Top-down Microarchitecture Analysis (TMA) method's slots where no micro-operations were being issued from front-end to back-end of the machine due to lack of back-end resources.",
> + "SampleAfterValue": "10000003",
> + "UMask": "0x2"
> + },
> + {
> + "BriefDescription": "TMA slots wasted due to incorrect speculation by branch mispredictions",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Number of TMA slots that were wasted due to incorrect speculation by branch mispredictions. This event estimates number of operations that were issued but not retired from the specualtive path as well as the out-of-order engine recovery past a branch misprediction.",
> + "SampleAfterValue": "10000003",
> + "UMask": "0x8"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "Fixed counter 3",
> + "EventName": "TOPDOWN.SLOTS",
> + "PEBScounters": "35",
> + "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core. Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
> + "SampleAfterValue": "10000003",
> + "UMask": "0x4"
> + },
> + {
> + "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
> + "CollectPEBSRecord": "2",
> + "Counter": "0,1,2,3,4,5,6,7",
> + "EventCode": "0xa4",
> + "EventName": "TOPDOWN.SLOTS_P",
> + "PEBScounters": "0,1,2,3,4,5,6,7",
> + "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method. The count is distributed among unhalted logical processors (hyper-threads) who share the same physical core.",
> + "SampleAfterValue": "10000003",
> + "UMask": "0x1"
> + },
> {
> "BriefDescription": "Number of uops decoded out of instructions exclusively fetched by decoder 0",
> "CollectPEBSRecord": "2",
--
Zhengjun Xing
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/8] perf vendor events: Update events for CascadelakeX
[not found] <20220317182858.484474-1-irogers@google.com>
` (5 preceding siblings ...)
2022-03-17 18:28 ` [PATCH 7/8] perf vendor events: Update events for Tigerlake Ian Rogers
@ 2022-03-18 9:14 ` John Garry
6 siblings, 0 replies; 13+ messages in thread
From: John Garry @ 2022-03-18 9:14 UTC (permalink / raw)
To: Ian Rogers, Kan Liang, Zhengjun Xing, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Mark Rutland, Alexander Shishkin,
Jiri Olsa, Namhyung Kim, Maxime Coquelin, Alexandre Torgue,
Andi Kleen, James Clark, linux-kernel, linux-perf-users
Cc: Stephane Eranian
On 17/03/2022 18:28, Ian Rogers wrote:
> The change:
> https://github.com/intel/event-converter-for-linux-perf/commit/fc680410402e394eed6a1ebd909c9f649d3ed3ef
> moved certain "other" type of events in to the cache topic. Update the
> perf json files for this change.
>
> Tested:
> ```
> ...
> 6: Parse event definition strings : Ok
> 7: Simple expression parser : Ok
> 8: PERF_RECORD_* events & perf_sample fields : Ok
> 9: Parse perf pmu format : Ok
> 10: PMU events :
> 10.1: PMU event table sanity : Ok
> 10.2: PMU event map aliases : Ok
> 10.3: Parsing of PMU event table metrics : Ok
> 10.4: Parsing of PMU event table metrics with fake PMUs : Ok
> ...
> 68: Parse and process metrics : Ok
> ...
> 89: perf all metricgroups test : Ok
> 90: perf all metrics test : FAILED!
> 91: perf all PMU test : Ok
> ...
> ```
>
> Test 90 failed due to MEM_PMM_Read_Latency as the test machine
> lacks optane memory, and the divide by 0 causes the metric not to
> print - which is intended behavior.
Hi Ian,
Failing is not ideal as an intended/expected behaviour. Could we make
the test skip somehow for the case you describe?
Thanks,
John
^ permalink raw reply [flat|nested] 13+ messages in thread