From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0557AC54EE9 for ; Mon, 19 Sep 2022 15:55:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230312AbiISPzX (ORCPT ); Mon, 19 Sep 2022 11:55:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230185AbiISPzV (ORCPT ); Mon, 19 Sep 2022 11:55:21 -0400 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 905B5E0F6; Mon, 19 Sep 2022 08:55:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663602919; x=1695138919; h=message-id:date:mime-version:to:cc:references:from: subject:in-reply-to:content-transfer-encoding; bh=/RZXgUps2cAXRsr5swlx+LTN2mlpIuZ511tKlfnJhwY=; b=NoTAIBv+JqnfSaNRAUaIw/xl3n0lMdoGU5AZApiGfUenb6dWaJIgdkFb 7WWa3CTGClogFeZRVMIHw5BDrh/n3u2xFoQDLUxRegs972cJG89WMUWcA 5IdJezvtYfAhlIUWqmE41CVZlFhfhw2lBkVfoSMVC7djEhapthPiAwWdb fsk/E5mrIkBiwkcJ74NaKJP4MqI8dQRfp58b/5uwruyRk18YI/1UWtiTu X5iCFJadOGkrQ60R8EkJdzP32tPX3XOyWMtpeW0JaELK/dPplXEu1yVtY BSpGaa7GnK9MFsBrBJM2wC8fuv0+xZYF3+04ywZ6ezneUvacx35DNuGS3 w==; X-IronPort-AV: E=McAfee;i="6500,9779,10475"; a="385725817" X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="385725817" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2022 08:55:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="651727338" Received: from linux.intel.com ([10.54.29.200]) by orsmga001.jf.intel.com with ESMTP; 19 Sep 2022 08:55:18 -0700 Received: from [10.252.210.144] (kliang2-mobl1.ccr.corp.intel.com [10.252.210.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by linux.intel.com (Postfix) with ESMTPS id 430BB580A31; Mon, 19 Sep 2022 08:55:17 -0700 (PDT) Message-ID: <0a5fdd6d-2207-d44f-2854-ec5882d557e7@linux.intel.com> Date: Mon, 19 Sep 2022 11:55:16 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Content-Language: en-US To: "Wang, Wei W" , "Li, Xiaoyao" , Peter Zijlstra , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , "Christopherson,, Sean" , Paolo Bonzini , "Liang, Kan" , "Kleen, Andi" Cc: "linux-perf-users@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" References: <20220825085625.867763-1-xiaoyao.li@intel.com> <815586ac-1eaa-5e38-1e08-492c29d0729d@intel.com> <4c6a5663-778e-a509-638c-92cfd5315274@linux.intel.com> From: "Liang, Kan" Subject: Re: [RFC PATCH 0/2] KVM: VMX: Fix VM entry failure on PT_MODE_HOST_GUEST while host is using PT In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On 2022-09-19 11:22 a.m., Wang, Wei W wrote: > On Monday, September 19, 2022 10:41 PM, Liang, Kan wrote: >> Another fake event? We have to specially handle it in the perf code. I don't >> think it's a clean way for perf. > > We can check the patch later. I think it should be clean, like the LBR side. I doubt. Perf already specially handles the fake LBR event in several places from the core code to the LBR code. It also occupy a reserved bit. If there is another choice, I don't think we want to go that way. > >> >>> - on VMEnter: >>> -- perf_disable_event_local(host_event); >>> -- perf_enable_event_local(guest_event); >>> - on VMExit: >>> -- perf_disable_event_local(guest_event); >>> -- perf_enable_event_local(host_event); >> >> Why we cannot use the same way as the perf core driver to switch the MSRs in >> the VMCS? > > The current MSR switching list from VMCS isn’t fast, > should be the last resort when really necessary. > It's a documented way in the SDM. I believe there must be some reason Intel introduces it. Since it's an documented (or recommended) way, I think we'd better use it if possible. Since both the PT and the core driver needs to switch MSRs during VMCS, it's better to use the same way (function) to handle them. Thanks, Kan >> >> You just need one generic function, perf_guest_get_msrs(), for both PT and >> core driver. If you have to disable PT explicitly before VMCS, I think you can do >> it in the PT specific perf_guest_get_msrs(). > > The disable is done via " Clear IA32_RTIT_CTL" VMExit control. > It can ensure PT disabled in time on VMExit, so no need to go through perf_guest_get_msrs. >