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X-CSE-ConnectionGUID: YuakE+m0T7mDNnZxEWKMkw== X-CSE-MsgGUID: /F8QrZDcQ6yEh+M837d9ZA== X-IronPort-AV: E=McAfee;i="6700,10204,11262"; a="42759341" X-IronPort-AV: E=Sophos;i="6.12,171,1728975600"; d="scan'208";a="42759341" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2024 19:25:03 -0800 X-CSE-ConnectionGUID: KKr9iwA0SiemQXoOJsMnqw== X-CSE-MsgGUID: zSInqAUfRqCX81ga2CQYmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,171,1728975600"; d="scan'208";a="90517877" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.245.128]) ([10.124.245.128]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Nov 2024 19:24:58 -0800 Message-ID: <0a761b20-dc5e-4bba-a72b-07627befc835@linux.intel.com> Date: Thu, 21 Nov 2024 11:24:55 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v3 52/58] KVM: x86/pmu/svm: Implement callback to disable MSR interception To: Sean Christopherson , Mingwei Zhang Cc: Paolo Bonzini , Xiong Zhang , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, Aaron Lewis References: <20240801045907.4010984-1-mizhang@google.com> <20240801045907.4010984-53-mizhang@google.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/21/2024 5:02 AM, Sean Christopherson wrote: > +Aaron > > On Thu, Aug 01, 2024, Mingwei Zhang wrote: >> +static void amd_passthrough_pmu_msrs(struct kvm_vcpu *vcpu) >> +{ >> + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); >> + struct vcpu_svm *svm = to_svm(vcpu); >> + int msr_clear = !!(is_passthrough_pmu_enabled(vcpu)); >> + int i; >> + >> + for (i = 0; i < min(pmu->nr_arch_gp_counters, AMD64_NUM_COUNTERS); i++) { >> + /* >> + * Legacy counters are always available irrespective of any >> + * CPUID feature bits and when X86_FEATURE_PERFCTR_CORE is set, >> + * PERF_LEGACY_CTLx and PERF_LEGACY_CTRx registers are mirrored >> + * with PERF_CTLx and PERF_CTRx respectively. >> + */ >> + set_msr_interception(vcpu, svm->msrpm, MSR_K7_EVNTSEL0 + i, 0, 0); >> + set_msr_interception(vcpu, svm->msrpm, MSR_K7_PERFCTR0 + i, msr_clear, msr_clear); >> + } >> + >> + for (i = 0; i < kvm_pmu_cap.num_counters_gp; i++) { >> + /* >> + * PERF_CTLx registers require interception in order to clear >> + * HostOnly bit and set GuestOnly bit. This is to prevent the >> + * PERF_CTRx registers from counting before VM entry and after >> + * VM exit. >> + */ >> + set_msr_interception(vcpu, svm->msrpm, MSR_F15H_PERF_CTL + 2 * i, 0, 0); >> + >> + /* >> + * Pass through counters exposed to the guest and intercept >> + * counters that are unexposed. Do this explicitly since this >> + * function may be set multiple times before vcpu runs. >> + */ >> + if (i >= pmu->nr_arch_gp_counters) >> + msr_clear = 0; > Similar to my comments on the Intel side, explicitly enable interception for > MSRs that don't exist in the guest model in a separate for-loop, i.e. don't > toggle msr_clear in the middle of a loop. Sure. > > I would also love to de-dup the bulk of this code, which is very doable since > the base+shift for the MSRs is going to be stashed in kvm_pmu. All that's needed > on top is unified MSR interception logic, which is something that's been on my > wish list for some time. SVM's inverted polarity needs to die a horrible death. > > Lucky for me, Aaron is picking up that torch. > > Aaron, what's your ETA on the MSR unification? No rush, but if you think it'll > be ready in the next month or so, I'll plan on merging that first and landing > this code on top. Is there a public link for Aaron's patches? If so, we can rebase the next version patches on top of Aaron's patches. > >> + set_msr_interception(vcpu, svm->msrpm, MSR_F15H_PERF_CTR + 2 * i, msr_clear, msr_clear); >> + } >> + >> + /* >> + * In mediated passthrough vPMU, intercept global PMU MSRs when guest >> + * PMU only owns a subset of counters provided in HW or its version is >> + * less than 2. >> + */ >> + if (is_passthrough_pmu_enabled(vcpu) && pmu->version > 1 && > kvm_pmu_has_perf_global_ctrl(), no? Yes. > >> + pmu->nr_arch_gp_counters == kvm_pmu_cap.num_counters_gp) >> + msr_clear = 1; >> + else >> + msr_clear = 0; >> + >> + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_CTL, msr_clear, msr_clear); >> + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, msr_clear, msr_clear); >> + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, msr_clear, msr_clear); >> + set_msr_interception(vcpu, svm->msrpm, MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_SET, msr_clear, msr_clear); >> +} >> + >> struct kvm_pmu_ops amd_pmu_ops __initdata = { >> .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, >> .msr_idx_to_pmc = amd_msr_idx_to_pmc, >> @@ -258,6 +312,7 @@ struct kvm_pmu_ops amd_pmu_ops __initdata = { >> .refresh = amd_pmu_refresh, >> .init = amd_pmu_init, >> .is_rdpmc_passthru_allowed = amd_is_rdpmc_passthru_allowed, >> + .passthrough_pmu_msrs = amd_passthrough_pmu_msrs, >> .EVENTSEL_EVENT = AMD64_EVENTSEL_EVENT, >> .MAX_NR_GP_COUNTERS = KVM_AMD_PMC_MAX_GENERIC, >> .MIN_NR_GP_COUNTERS = AMD64_NUM_COUNTERS, >> -- >> 2.46.0.rc1.232.g9752f9e123-goog >>