* [PATCH] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR
@ 2024-02-14 15:57 kan.liang
2024-02-14 23:45 ` Ian Rogers
0 siblings, 1 reply; 3+ messages in thread
From: kan.liang @ 2024-02-14 15:57 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung, linux-kernel, linux-perf-users
Cc: irogers, mpetlan, eranian, ak, Kan Liang, stable
From: Kan Liang <kan.liang@linux.intel.com>
The perf stat errors out with UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL
event.
$perf stat -e uncore_cha_55/event=0x35,umask=0x10c0008101/ -a -- ls
event syntax error: '..0x35,umask=0x10c0008101/'
\___ Bad event or PMU
The definition of the CHA umask is config:8-15,32-55, which is 32bit.
However, the umask of the event is bigger than 32bit.
This is an error in the original uncore spec.
Add a new umask_ext5 for the new CHA umask range.
Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
Closes: https://lore.kernel.org/linux-perf-users/alpine.LRH.2.20.2401300733310.11354@Diego/
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: stable@vger.kernel.org
---
arch/x86/events/intel/uncore_snbep.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
index a96496bef678..7924f315269a 100644
--- a/arch/x86/events/intel/uncore_snbep.c
+++ b/arch/x86/events/intel/uncore_snbep.c
@@ -461,6 +461,7 @@
#define SPR_UBOX_DID 0x3250
/* SPR CHA */
+#define SPR_CHA_EVENT_MASK_EXT 0xffffffff
#define SPR_CHA_PMON_CTL_TID_EN (1 << 16)
#define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
SPR_CHA_PMON_CTL_TID_EN)
@@ -477,6 +478,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55");
DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57");
DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39");
DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55");
+DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63");
DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
@@ -5957,7 +5959,7 @@ static struct intel_uncore_ops spr_uncore_chabox_ops = {
static struct attribute *spr_uncore_cha_formats_attr[] = {
&format_attr_event.attr,
- &format_attr_umask_ext4.attr,
+ &format_attr_umask_ext5.attr,
&format_attr_tid_en2.attr,
&format_attr_edge.attr,
&format_attr_inv.attr,
@@ -5993,7 +5995,7 @@ ATTRIBUTE_GROUPS(uncore_alias);
static struct intel_uncore_type spr_uncore_chabox = {
.name = "cha",
.event_mask = SPR_CHA_PMON_EVENT_MASK,
- .event_mask_ext = SPR_RAW_EVENT_MASK_EXT,
+ .event_mask_ext = SPR_CHA_EVENT_MASK_EXT,
.num_shared_regs = 1,
.constraints = skx_uncore_chabox_constraints,
.ops = &spr_uncore_chabox_ops,
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR
2024-02-14 15:57 [PATCH] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR kan.liang
@ 2024-02-14 23:45 ` Ian Rogers
2024-03-18 17:18 ` Liang, Kan
0 siblings, 1 reply; 3+ messages in thread
From: Ian Rogers @ 2024-02-14 23:45 UTC (permalink / raw)
To: kan.liang
Cc: peterz, mingo, acme, namhyung, linux-kernel, linux-perf-users,
mpetlan, eranian, ak, stable
On Wed, Feb 14, 2024 at 7:58 AM <kan.liang@linux.intel.com> wrote:
>
> From: Kan Liang <kan.liang@linux.intel.com>
>
> The perf stat errors out with UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL
> event.
>
> $perf stat -e uncore_cha_55/event=0x35,umask=0x10c0008101/ -a -- ls
> event syntax error: '..0x35,umask=0x10c0008101/'
> \___ Bad event or PMU
>
> The definition of the CHA umask is config:8-15,32-55, which is 32bit.
> However, the umask of the event is bigger than 32bit.
> This is an error in the original uncore spec.
>
> Add a new umask_ext5 for the new CHA umask range.
>
> Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
> Closes: https://lore.kernel.org/linux-perf-users/alpine.LRH.2.20.2401300733310.11354@Diego/
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
> Cc: stable@vger.kernel.org
Reviewed-by: Ian Rogers <irogers@google.com>
Thanks,
Ian
> ---
> arch/x86/events/intel/uncore_snbep.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
> index a96496bef678..7924f315269a 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -461,6 +461,7 @@
> #define SPR_UBOX_DID 0x3250
>
> /* SPR CHA */
> +#define SPR_CHA_EVENT_MASK_EXT 0xffffffff
> #define SPR_CHA_PMON_CTL_TID_EN (1 << 16)
> #define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
> SPR_CHA_PMON_CTL_TID_EN)
> @@ -477,6 +478,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55");
> DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57");
> DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39");
> DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55");
> +DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63");
> DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
> DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
> DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
> @@ -5957,7 +5959,7 @@ static struct intel_uncore_ops spr_uncore_chabox_ops = {
>
> static struct attribute *spr_uncore_cha_formats_attr[] = {
> &format_attr_event.attr,
> - &format_attr_umask_ext4.attr,
> + &format_attr_umask_ext5.attr,
> &format_attr_tid_en2.attr,
> &format_attr_edge.attr,
> &format_attr_inv.attr,
> @@ -5993,7 +5995,7 @@ ATTRIBUTE_GROUPS(uncore_alias);
> static struct intel_uncore_type spr_uncore_chabox = {
> .name = "cha",
> .event_mask = SPR_CHA_PMON_EVENT_MASK,
> - .event_mask_ext = SPR_RAW_EVENT_MASK_EXT,
> + .event_mask_ext = SPR_CHA_EVENT_MASK_EXT,
> .num_shared_regs = 1,
> .constraints = skx_uncore_chabox_constraints,
> .ops = &spr_uncore_chabox_ops,
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR
2024-02-14 23:45 ` Ian Rogers
@ 2024-03-18 17:18 ` Liang, Kan
0 siblings, 0 replies; 3+ messages in thread
From: Liang, Kan @ 2024-03-18 17:18 UTC (permalink / raw)
To: Ingo Molnar
Cc: peterz, acme, namhyung, linux-kernel, linux-perf-users, mpetlan,
eranian, ak, stable, Ian Rogers
On 2024-02-14 6:45 p.m., Ian Rogers wrote:
> On Wed, Feb 14, 2024 at 7:58 AM <kan.liang@linux.intel.com> wrote:
>>
>> From: Kan Liang <kan.liang@linux.intel.com>
>>
>> The perf stat errors out with UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL
>> event.
>>
>> $perf stat -e uncore_cha_55/event=0x35,umask=0x10c0008101/ -a -- ls
>> event syntax error: '..0x35,umask=0x10c0008101/'
>> \___ Bad event or PMU
>>
>> The definition of the CHA umask is config:8-15,32-55, which is 32bit.
>> However, the umask of the event is bigger than 32bit.
>> This is an error in the original uncore spec.
>>
>> Add a new umask_ext5 for the new CHA umask range.
>>
>> Fixes: 949b11381f81 ("perf/x86/intel/uncore: Add Sapphire Rapids server CHA support")
>> Closes: https://lore.kernel.org/linux-perf-users/alpine.LRH.2.20.2401300733310.11354@Diego/
>> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
>> Cc: stable@vger.kernel.org
>
> Reviewed-by: Ian Rogers <irogers@google.com>
Hi Ingo,
Could you please take a look at the patch? If it's OK for you, could you
please merge the fix?
Thanks,
Kan
>
> Thanks,
> Ian
>
>> ---
>> arch/x86/events/intel/uncore_snbep.c | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c
>> index a96496bef678..7924f315269a 100644
>> --- a/arch/x86/events/intel/uncore_snbep.c
>> +++ b/arch/x86/events/intel/uncore_snbep.c
>> @@ -461,6 +461,7 @@
>> #define SPR_UBOX_DID 0x3250
>>
>> /* SPR CHA */
>> +#define SPR_CHA_EVENT_MASK_EXT 0xffffffff
>> #define SPR_CHA_PMON_CTL_TID_EN (1 << 16)
>> #define SPR_CHA_PMON_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
>> SPR_CHA_PMON_CTL_TID_EN)
>> @@ -477,6 +478,7 @@ DEFINE_UNCORE_FORMAT_ATTR(umask_ext, umask, "config:8-15,32-43,45-55");
>> DEFINE_UNCORE_FORMAT_ATTR(umask_ext2, umask, "config:8-15,32-57");
>> DEFINE_UNCORE_FORMAT_ATTR(umask_ext3, umask, "config:8-15,32-39");
>> DEFINE_UNCORE_FORMAT_ATTR(umask_ext4, umask, "config:8-15,32-55");
>> +DEFINE_UNCORE_FORMAT_ATTR(umask_ext5, umask, "config:8-15,32-63");
>> DEFINE_UNCORE_FORMAT_ATTR(qor, qor, "config:16");
>> DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
>> DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
>> @@ -5957,7 +5959,7 @@ static struct intel_uncore_ops spr_uncore_chabox_ops = {
>>
>> static struct attribute *spr_uncore_cha_formats_attr[] = {
>> &format_attr_event.attr,
>> - &format_attr_umask_ext4.attr,
>> + &format_attr_umask_ext5.attr,
>> &format_attr_tid_en2.attr,
>> &format_attr_edge.attr,
>> &format_attr_inv.attr,
>> @@ -5993,7 +5995,7 @@ ATTRIBUTE_GROUPS(uncore_alias);
>> static struct intel_uncore_type spr_uncore_chabox = {
>> .name = "cha",
>> .event_mask = SPR_CHA_PMON_EVENT_MASK,
>> - .event_mask_ext = SPR_RAW_EVENT_MASK_EXT,
>> + .event_mask_ext = SPR_CHA_EVENT_MASK_EXT,
>> .num_shared_regs = 1,
>> .constraints = skx_uncore_chabox_constraints,
>> .ops = &spr_uncore_chabox_ops,
>> --
>> 2.35.1
>>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-02-14 15:57 [PATCH] perf/x86/intel/uncore: Fix the bits of the CHA extended umask for SPR kan.liang
2024-02-14 23:45 ` Ian Rogers
2024-03-18 17:18 ` Liang, Kan
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