From: Jing Zhang <renyu.zj@linux.alibaba.com>
To: John Garry <john.g.garry@oracle.com>,
Ian Rogers <irogers@google.com>,
Xing Zhengjun <zhengjun.xing@linux.intel.com>,
Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>,
Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
Andrew Kilroy <andrew.kilroy@arm.com>,
Shuai Xue <xueshuai@linux.alibaba.com>,
Zhuo Song <zhuo.song@linux.alibaba.com>,
Jing Zhang <renyu.zj@linux.alibaba.com>
Subject: [PATCH v5 3/6] perf vendor events arm64: Add cache metrics for neoverse-n2
Date: Tue, 3 Jan 2023 19:39:33 +0800 [thread overview]
Message-ID: <1672745976-2800146-4-git-send-email-renyu.zj@linux.alibaba.com> (raw)
In-Reply-To: <1672745976-2800146-1-git-send-email-renyu.zj@linux.alibaba.com>
Add cache related metrics.
Signed-off-by: Jing Zhang <renyu.zj@linux.alibaba.com>
Acked-by: Ian Rogers <irogers@google.com>
---
.../arch/arm64/arm/neoverse-n2/metrics.json | 77 ++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json
index 8a74e07..f81b40d 100644
--- a/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json
+++ b/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2/metrics.json
@@ -75,5 +75,82 @@
"MetricGroup": "TLB",
"MetricName": "itlb_walk_rate",
"ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "L1I_CACHE_REFILL / INST_RETIRED * 1000",
+ "BriefDescription": "The rate of L1 I-Cache misses per kilo instructions",
+ "MetricGroup": "Cache",
+ "MetricName": "l1i_cache_mpki",
+ "ScaleUnit": "MPKI"
+ },
+ {
+ "MetricExpr": "L1I_CACHE_REFILL / L1I_CACHE",
+ "BriefDescription": "The rate of L1 I-Cache misses to the overall L1 I-Cache",
+ "MetricGroup": "Cache",
+ "MetricName": "l1i_cache_miss_rate",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "L1D_CACHE_REFILL / INST_RETIRED * 1000",
+ "BriefDescription": "The rate of L1 D-Cache misses per kilo instructions",
+ "MetricGroup": "Cache",
+ "MetricName": "l1d_cache_mpki",
+ "ScaleUnit": "MPKI"
+ },
+ {
+ "MetricExpr": "L1D_CACHE_REFILL / L1D_CACHE",
+ "BriefDescription": "The rate of L1 D-Cache misses to the overall L1 D-Cache",
+ "MetricGroup": "Cache",
+ "MetricName": "l1d_cache_miss_rate",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "L2D_CACHE_REFILL / INST_RETIRED * 1000",
+ "BriefDescription": "The rate of L2 D-Cache misses per kilo instructions",
+ "MetricGroup": "Cache",
+ "MetricName": "l2d_cache_mpki",
+ "ScaleUnit": "MPKI"
+ },
+ {
+ "MetricExpr": "L2D_CACHE_REFILL / L2D_CACHE",
+ "BriefDescription": "The rate of L2 D-Cache misses to the overall L2 D-Cache",
+ "MetricGroup": "Cache",
+ "MetricName": "l2d_cache_miss_rate",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "L3D_CACHE_REFILL / INST_RETIRED * 1000",
+ "BriefDescription": "The rate of L3 D-Cache misses per kilo instructions",
+ "MetricGroup": "Cache",
+ "MetricName": "l3d_cache_mpki",
+ "ScaleUnit": "MPKI"
+ },
+ {
+ "MetricExpr": "L3D_CACHE_REFILL / L3D_CACHE",
+ "BriefDescription": "The rate of L3 D-Cache misses to the overall L3 D-Cache",
+ "MetricGroup": "Cache",
+ "MetricName": "l3d_cache_miss_rate",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "LL_CACHE_MISS_RD / INST_RETIRED * 1000",
+ "BriefDescription": "The rate of LL Cache read misses per kilo instructions",
+ "MetricGroup": "Cache",
+ "MetricName": "ll_cache_read_mpki",
+ "ScaleUnit": "MPKI"
+ },
+ {
+ "MetricExpr": "LL_CACHE_MISS_RD / LL_CACHE_RD",
+ "BriefDescription": "The rate of LL Cache read misses to the overall LL Cache read",
+ "MetricGroup": "Cache",
+ "MetricName": "ll_cache_read_miss_rate",
+ "ScaleUnit": "100%"
+ },
+ {
+ "MetricExpr": "(LL_CACHE_RD - LL_CACHE_MISS_RD) / LL_CACHE_RD",
+ "BriefDescription": "The rate of LL Cache read hit to the overall LL Cache read",
+ "MetricGroup": "Cache",
+ "MetricName": "ll_cache_read_hit_rate",
+ "ScaleUnit": "100%"
}
]
--
1.8.3.1
next prev parent reply other threads:[~2023-01-03 11:40 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-03 11:39 [PATCH v5 0/6] Add metrics for neoverse-n2 Jing Zhang
2023-01-03 11:39 ` [PATCH v5 1/6] perf vendor events arm64: Add topdown L1 " Jing Zhang
2023-01-03 11:52 ` John Garry
2023-01-04 5:05 ` Jing Zhang
2023-01-04 17:26 ` John Garry
2023-01-05 10:05 ` Jing Zhang
2023-01-05 10:13 ` John Garry
2023-01-05 11:02 ` Jing Zhang
2023-01-05 21:13 ` Ian Rogers
2023-01-06 10:14 ` John Garry
2023-01-06 10:34 ` Jing Zhang
2023-01-09 15:34 ` James Clark
2023-01-11 6:14 ` Ian Rogers
2023-01-03 11:39 ` [PATCH v5 2/6] perf vendor events arm64: Add TLB " Jing Zhang
2023-01-03 17:14 ` Ian Rogers
2023-01-04 5:21 ` Jing Zhang
2023-01-04 8:40 ` Jing Zhang
2023-01-04 16:57 ` Ian Rogers
2023-01-03 11:39 ` Jing Zhang [this message]
2023-01-03 11:39 ` [PATCH v5 4/6] perf vendor events arm64: Add branch " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 5/6] perf vendor events arm64: Add PE utilization " Jing Zhang
2023-01-03 11:39 ` [PATCH v5 6/6] perf vendor events arm64: Add instruction mix " Jing Zhang
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