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Fri, 14 Feb 2025 02:02:49 -0800 (PST) Received: from [192.168.68.163] ([145.224.90.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4396b5267b6sm1615605e9.0.2025.02.14.02.02.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 14 Feb 2025 02:02:47 -0800 (PST) Message-ID: <1b8b234f-6435-45cf-83e7-8e86c84f075f@linaro.org> Date: Fri, 14 Feb 2025 10:02:44 +0000 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/2] perf vendor events arm64: Add A720/A520 events/metrics To: Yangyu Chen , Namhyung Kim , Ian Rogers Cc: linux-perf-users@vger.kernel.org, John Garry , Will Deacon , Mike Leach , Leo Yan , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Mark Rutland , Alexander Shishkin , Jiri Olsa , Adrian Hunter , Liang Kan , Yoshihiro Furudera , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: Content-Language: en-US From: James Clark In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 14/02/2025 5:49 am, Yangyu Chen wrote: > > >> On 14 Feb 2025, at 09:12, Namhyung Kim wrote: >> >> Hello, >> >> On Thu, Feb 13, 2025 at 11:11:01PM +0800, Yangyu Chen wrote: >>> This patchset adds the perf JSON files for the Cortex-A720 and Cortex-A520 >>> processors. Some events have been tested on Raxda Orion 6 with Cix P1 SoC >>> (8xA720 + 4xA520) running mainline Kernel with ACPI mode. >> >> I'm curious how the name of PMUs look like. It is cortex_a720 (or a520)? > > The name of PMUs comes from Arm's documentation. I have included these > links in each patch. > >> I remember there's a logic to check the length of hex digits at the end. >> > > Could you provide more details about this? > >> Ian, are you ok with this? >> I think they wouldn't be merged because they're core PMUs, so should be fine? Even though they would otherwise be merged because they're more than 3 hex digits. >> Thanks, >> Namhyung >> >>> >>> Yangyu Chen (2): >>> perf vendor events arm64: Add Cortex-A720 events/metrics >>> perf vendor events arm64: Add Cortex-A520 events/metrics >>> >>> .../arch/arm64/arm/cortex-a520/bus.json | 26 ++ >>> .../arch/arm64/arm/cortex-a520/exception.json | 18 + >>> .../arm64/arm/cortex-a520/fp_operation.json | 14 + >>> .../arch/arm64/arm/cortex-a520/general.json | 6 + >>> .../arch/arm64/arm/cortex-a520/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a520/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a520/l2_cache.json | 46 ++ >>> .../arch/arm64/arm/cortex-a520/l3_cache.json | 21 + >>> .../arch/arm64/arm/cortex-a520/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a520/memory.json | 58 +++ >>> .../arch/arm64/arm/cortex-a520/metrics.json | 373 +++++++++++++++ >>> .../arch/arm64/arm/cortex-a520/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a520/retired.json | 90 ++++ >>> .../arm64/arm/cortex-a520/spec_operation.json | 70 +++ >>> .../arch/arm64/arm/cortex-a520/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a520/sve.json | 22 + >>> .../arch/arm64/arm/cortex-a520/tlb.json | 78 ++++ >>> .../arch/arm64/arm/cortex-a520/trace.json | 32 ++ >>> .../arch/arm64/arm/cortex-a720/bus.json | 18 + >>> .../arch/arm64/arm/cortex-a720/exception.json | 62 +++ >>> .../arm64/arm/cortex-a720/fp_operation.json | 22 + >>> .../arch/arm64/arm/cortex-a720/general.json | 10 + >>> .../arch/arm64/arm/cortex-a720/l1d_cache.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/l1i_cache.json | 14 + >>> .../arch/arm64/arm/cortex-a720/l2_cache.json | 62 +++ >>> .../arch/arm64/arm/cortex-a720/l3_cache.json | 22 + >>> .../arch/arm64/arm/cortex-a720/ll_cache.json | 10 + >>> .../arch/arm64/arm/cortex-a720/memory.json | 54 +++ >>> .../arch/arm64/arm/cortex-a720/metrics.json | 436 ++++++++++++++++++ >>> .../arch/arm64/arm/cortex-a720/pmu.json | 8 + >>> .../arch/arm64/arm/cortex-a720/retired.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/spe.json | 42 ++ >>> .../arm64/arm/cortex-a720/spec_operation.json | 90 ++++ >>> .../arch/arm64/arm/cortex-a720/stall.json | 82 ++++ >>> .../arch/arm64/arm/cortex-a720/sve.json | 50 ++ >>> .../arch/arm64/arm/cortex-a720/tlb.json | 74 +++ >>> .../arch/arm64/arm/cortex-a720/trace.json | 32 ++ >>> .../arch/arm64/common-and-microarch.json | 15 + >>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 2 + >>> 39 files changed, 2263 insertions(+) >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a520/trace.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/bus.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/exception.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/fp_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/general.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1d_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l1i_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l2_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/l3_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/ll_cache.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/memory.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/metrics.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/pmu.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/retired.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spe.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/spec_operation.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/stall.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/sve.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/tlb.json >>> create mode 100644 tools/perf/pmu-events/arch/arm64/arm/cortex-a720/trace.json >>> >>> -- >>> 2.47.2 >>> >