* [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N
@ 2022-11-18 7:56 zhengjun.xing
2022-11-18 7:56 ` [PATCH 2/5] perf vendor events intel: Add core event list " zhengjun.xing
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: zhengjun.xing @ 2022-11-18 7:56 UTC (permalink / raw)
To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung
Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang,
zhengjun.xing
From: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Alderlake-N only has E-core, it has been moved to non-hybrid code path on
the kernel side, add the cpuid for Alderlake-N separately. Both events for
Alderlake and Alderlake-N are based on JSON file v1.16.
Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 5e609b876790..df47462a125f 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,5 +1,6 @@
Family-model,Version,Filename,EventType
-GenuineIntel-6-(97|9A|B7|BA|BE|BF),v1.15,alderlake,core
+GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core
+GenuineIntel-6-BE,v1.16,alderlaken,core
GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core
GenuineIntel-6-(3D|47),v26,broadwell,core
GenuineIntel-6-56,v23,broadwellde,core
--
2.25.1
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH 2/5] perf vendor events intel: Add core event list for Alderlake-N 2022-11-18 7:56 [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N zhengjun.xing @ 2022-11-18 7:56 ` zhengjun.xing 2022-11-19 1:01 ` Ian Rogers 2022-11-18 7:57 ` [PATCH 3/5] perf vendor events intel: Add uncore " zhengjun.xing ` (2 subsequent siblings) 3 siblings, 1 reply; 7+ messages in thread From: zhengjun.xing @ 2022-11-18 7:56 UTC (permalink / raw) To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang, zhengjun.xing From: Zhengjun Xing <zhengjun.xing@linux.intel.com> Alderlake-N only has E-core, it has been moved to non-hybrid code path on the kernel side. Add core event list for Alderlake-N, it is based on the ADL gracemont v1.16 JSON file. https://github.com/intel/perfmon/tree/main/ADL/events/ Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- .../pmu-events/arch/x86/alderlaken/cache.json | 450 ++++++++++ .../arch/x86/alderlaken/floating-point.json | 25 + .../arch/x86/alderlaken/frontend.json | 38 + .../arch/x86/alderlaken/memory.json | 109 +++ .../pmu-events/arch/x86/alderlaken/other.json | 42 + .../arch/x86/alderlaken/pipeline.json | 774 ++++++++++++++++++ .../arch/x86/alderlaken/virtual-memory.json | 71 ++ 7 files changed, 1509 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/cache.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/frontend.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/memory.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/other.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json new file mode 100644 index 000000000000..a6aa87d1365b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json @@ -0,0 +1,450 @@ +[ + { + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.MISS", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x2e", + "EventName": "LONGEST_LAT_CACHE.REFERENCE", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4f" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x38" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x34", + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.RSV", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x04", + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of load uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of load uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x81" + }, + { + "BriefDescription": "Counts the number of store uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of store uops retired.", + "SampleAfterValue": "200003", + "UMask": "0x82" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x80", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x10", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x100", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x20", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x4", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x200", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x40", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", + "L1_Hit_Indication": "1", + "MSRIndex": "0x3F6", + "MSRValue": "0x8", + "PEBS": "2", + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "TakenAlone": "1", + "UMask": "0x5" + }, + { + "BriefDescription": "Counts the number of retired split load uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x41" + }, + { + "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", + "L1_Hit_Indication": "1", + "PEBS": "2", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x4003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ICACHE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x20" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json new file mode 100644 index 000000000000..02eb1af8db00 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json @@ -0,0 +1,25 @@ +[ + { + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.FP_ASSIST", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.FPDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x8" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json new file mode 100644 index 000000000000..ed0587945a05 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json @@ -0,0 +1,38 @@ +[ + { + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xe6", + "EventName": "BACLEARS.ANY", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "100003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x80", + "EventName": "ICACHE.ACCESSES", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of instruction cache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x80", + "EventName": "ICACHE.MISSES", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json new file mode 100644 index 000000000000..cabf2fc8600f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json @@ -0,0 +1,109 @@ +[ + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.ANY_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xff" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.L1_BOUND_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xf4" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.OTHER_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xc0" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.PGWALK_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0xa0" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.ST_ADDR_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x84" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F84400002", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/other.json b/tools/perf/pmu-events/arch/x86/alderlaken/other.json new file mode 100644 index 000000000000..25c7f1f47e28 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/other.json @@ -0,0 +1,42 @@ +[ + { + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.COREWB_M.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10008", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json new file mode 100644 index 000000000000..f922d96e5aaa --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json @@ -0,0 +1,774 @@ +[ + { + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf9" + }, + { + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xbf" + }, + { + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of near CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf9" + }, + { + "BriefDescription": "Counts the number of near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.REL_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfd" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", + "SampleAfterValue": "200003" + }, + { + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.IND_CALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfb" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0x7e" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xeb" + }, + { + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RETURN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xf7" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "200003", + "UMask": "0xfe" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.CORE", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.CORE_P", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 2", + "EventName": "CPU_CLK_UNHALTED.REF_TSC", + "PEBScounters": "34", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 1", + "EventName": "CPU_CLK_UNHALTED.THREAD", + "PEBScounters": "33", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of unhalted core clock cycles.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.THREAD_P", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003", + "Speculative": "1" + }, + { + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", + "CollectPEBSRecord": "2", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.ANY", + "PEBS": "1", + "PEBScounters": "32", + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of instructions retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.ANY_P", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "Deprecated": "1", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.4K_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.DATA_UNKNOWN", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of machines clears due to memory renaming.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MRN_NUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.PAGE_FAULT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SLOW", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x6f" + }, + { + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "20003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x75", + "EventName": "SERIALIZATION.NON_C01_MS_SCB", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "SampleAfterValue": "1000003", + "Speculative": "1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x73", + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REGISTER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x74", + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ALL", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.CISC", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.DECODE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x8d" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x72" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.ITLB", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.OTHER", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x71", + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the total number of consumed retirement slots.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "TOPDOWN_RETIRING.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003" + }, + { + "BriefDescription": "Counts the total number of uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.ALL", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003" + }, + { + "BriefDescription": "Counts the number of integer divide uops retired.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.IDIV", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.X87", + "PEBS": "1", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "UMask": "0x2" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json new file mode 100644 index 000000000000..77f80d1a7cd4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json @@ -0,0 +1,71 @@ +[ + { + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x08", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x49", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "2000003", + "Speculative": "1", + "UMask": "0x80" + }, + { + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x85", + "EventName": "ITLB_MISSES.WALK_COMPLETED", + "PEBScounters": "0,1,2,3,4,5", + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", + "SampleAfterValue": "200003", + "Speculative": "1", + "UMask": "0xe" + }, + { + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", + "CollectPEBSRecord": "2", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x05", + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", + "PEBScounters": "0,1,2,3,4,5", + "SampleAfterValue": "1000003", + "Speculative": "1", + "UMask": "0x90" + } +] -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/5] perf vendor events intel: Add core event list for Alderlake-N 2022-11-18 7:56 ` [PATCH 2/5] perf vendor events intel: Add core event list " zhengjun.xing @ 2022-11-19 1:01 ` Ian Rogers 2022-11-21 2:59 ` Xing Zhengjun 0 siblings, 1 reply; 7+ messages in thread From: Ian Rogers @ 2022-11-19 1:01 UTC (permalink / raw) To: zhengjun.xing Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On Thu, Nov 17, 2022 at 11:57 PM <zhengjun.xing@linux.intel.com> wrote: > > From: Zhengjun Xing <zhengjun.xing@linux.intel.com> > > Alderlake-N only has E-core, it has been moved to non-hybrid code path on > the kernel side. Add core event list for Alderlake-N, it is based on the > ADL gracemont v1.16 JSON file. > > https://github.com/intel/perfmon/tree/main/ADL/events/ > > Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > Reviewed-by: Kan Liang <kan.liang@linux.intel.com> > --- > .../pmu-events/arch/x86/alderlaken/cache.json | 450 ++++++++++ > .../arch/x86/alderlaken/floating-point.json | 25 + > .../arch/x86/alderlaken/frontend.json | 38 + > .../arch/x86/alderlaken/memory.json | 109 +++ > .../pmu-events/arch/x86/alderlaken/other.json | 42 + > .../arch/x86/alderlaken/pipeline.json | 774 ++++++++++++++++++ > .../arch/x86/alderlaken/virtual-memory.json | 71 ++ > 7 files changed, 1509 insertions(+) > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/cache.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/frontend.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/memory.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/other.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json > create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json > > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json > new file mode 100644 > index 000000000000..a6aa87d1365b > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json > @@ -0,0 +1,450 @@ > +[ > + { > + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x2e", > + "EventName": "LONGEST_LAT_CACHE.MISS", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x41" In this event CollectPEBSRecord, Counter, PEBScounters and Speculative are all unused in the jevents.py converter. There is a new perf json creating tool that doesn't generate these unneeded values: https://github.com/intel/perfmon/pull/27 Would it not make more sense to use that to generate the AlderlakeN data? It also fixes a number of bugs, in particular in uncore event generation. Thanks, Ian > + }, > + { > + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x2e", > + "EventName": "LONGEST_LAT_CACHE.REFERENCE", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x4f" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.IFETCH", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x38" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x20" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.LOAD", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x7" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x34", > + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd1", > + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd1", > + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd1", > + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x04", > + "EventName": "MEM_SCHEDULER_BLOCK.ALL", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x7" > + }, > + { > + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x04", > + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x04", > + "EventName": "MEM_SCHEDULER_BLOCK.RSV", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x04", > + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of load uops retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of load uops retired.", > + "SampleAfterValue": "200003", > + "UMask": "0x81" > + }, > + { > + "BriefDescription": "Counts the number of store uops retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of store uops retired.", > + "SampleAfterValue": "200003", > + "UMask": "0x82" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x80", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x10", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x100", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x20", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x4", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x200", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x40", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", > + "L1_Hit_Indication": "1", > + "MSRIndex": "0x3F6", > + "MSRValue": "0x8", > + "PEBS": "2", > + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "TakenAlone": "1", > + "UMask": "0x5" > + }, > + { > + "BriefDescription": "Counts the number of retired split load uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x41" > + }, > + { > + "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Data_LA": "1", > + "EventCode": "0xd0", > + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", > + "L1_Hit_Indication": "1", > + "PEBS": "2", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.", > + "SampleAfterValue": "1000003", > + "UMask": "0x6" > + }, > + { > + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x4003C0001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x8003C0001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F803C0002", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10003C0002", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ICACHE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x20" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json > new file mode 100644 > index 000000000000..02eb1af8db00 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json > @@ -0,0 +1,25 @@ > +[ > + { > + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.FP_ASSIST", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.FPDIV", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "2000003", > + "UMask": "0x8" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json > new file mode 100644 > index 000000000000..ed0587945a05 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json > @@ -0,0 +1,38 @@ > +[ > + { > + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xe6", > + "EventName": "BACLEARS.ANY", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "SampleAfterValue": "100003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x80", > + "EventName": "ICACHE.ACCESSES", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x3" > + }, > + { > + "BriefDescription": "Counts the number of instruction cache misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x80", > + "EventName": "ICACHE.MISSES", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x2" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json > new file mode 100644 > index 000000000000..cabf2fc8600f > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json > @@ -0,0 +1,109 @@ > +[ > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.ANY_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0xff" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.L1_BOUND_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0xf4" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.OTHER_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0xc0" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.PGWALK_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0xa0" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.ST_ADDR_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x84" > + }, > + { > + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F84400001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F84400001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_RFO.L3_MISS", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F84400002", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x3F84400002", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/other.json b/tools/perf/pmu-events/arch/x86/alderlaken/other.json > new file mode 100644 > index 000000000000..25c7f1f47e28 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/other.json > @@ -0,0 +1,42 @@ > +[ > + { > + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.COREWB_M.ANY_RESPONSE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10008", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand data reads that have any type of response.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10001", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10002", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts streaming stores that have any type of response.", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xB7", > + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", > + "MSRIndex": "0x1a6,0x1a7", > + "MSRValue": "0x10800", > + "SampleAfterValue": "100003", > + "UMask": "0x1" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json > new file mode 100644 > index 000000000000..f922d96e5aaa > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json > @@ -0,0 +1,774 @@ > +[ > + { > + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", > + "SampleAfterValue": "200003" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xf9" > + }, > + { > + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.COND", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x7e" > + }, > + { > + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.COND_TAKEN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfe" > + }, > + { > + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.FAR_BRANCH", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xbf" > + }, > + { > + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.INDIRECT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xeb" > + }, > + { > + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfb" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.IND_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfb" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.JCC", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x7e" > + }, > + { > + "BriefDescription": "Counts the number of near CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.NEAR_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xf9" > + }, > + { > + "BriefDescription": "Counts the number of near RET branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.NEAR_RETURN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xf7" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xeb" > + }, > + { > + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.REL_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfd" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.RETURN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xf7" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc4", > + "EventName": "BR_INST_RETIRED.TAKEN_JCC", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfe" > + }, > + { > + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", > + "SampleAfterValue": "200003" > + }, > + { > + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.COND", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x7e" > + }, > + { > + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.COND_TAKEN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfe" > + }, > + { > + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.INDIRECT", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xeb" > + }, > + { > + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfb" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.IND_CALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfb" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.JCC", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0x7e" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xeb" > + }, > + { > + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.RETURN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xf7" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0xc5", > + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "200003", > + "UMask": "0xfe" > + }, > + { > + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 1", > + "EventName": "CPU_CLK_UNHALTED.CORE", > + "PEBScounters": "33", > + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of unhalted core clock cycles.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x3c", > + "EventName": "CPU_CLK_UNHALTED.CORE_P", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", > + "SampleAfterValue": "2000003", > + "Speculative": "1" > + }, > + { > + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 2", > + "EventName": "CPU_CLK_UNHALTED.REF_TSC", > + "PEBScounters": "34", > + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0x3" > + }, > + { > + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x3c", > + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 1", > + "EventName": "CPU_CLK_UNHALTED.THREAD", > + "PEBScounters": "33", > + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of unhalted core clock cycles.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x3c", > + "EventName": "CPU_CLK_UNHALTED.THREAD_P", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", > + "SampleAfterValue": "2000003", > + "Speculative": "1" > + }, > + { > + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", > + "CollectPEBSRecord": "2", > + "Counter": "Fixed counter 0", > + "EventName": "INST_RETIRED.ANY", > + "PEBS": "1", > + "PEBScounters": "32", > + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the total number of instructions retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc0", > + "EventName": "INST_RETIRED.ANY_P", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.", > + "SampleAfterValue": "2000003" > + }, > + { > + "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "Deprecated": "1", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.4K_ALIAS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x03", > + "EventName": "LD_BLOCKS.DATA_UNKNOWN", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of machines clears due to memory renaming.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.MRN_NUKE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.PAGE_FAULT", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x20" > + }, > + { > + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.SLOW", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x6f" > + }, > + { > + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc3", > + "EventName": "MACHINE_CLEARS.SMC", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "20003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x75", > + "EventName": "SERIALIZATION.NON_C01_MS_SCB", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", > + "SampleAfterValue": "1000003", > + "Speculative": "1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x3" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x73", > + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALL", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REGISTER", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x20" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x74", > + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ALL", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x2" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x40" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.CISC", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.DECODE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x8" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x8d" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x72" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.ITLB", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.OTHER", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x71", > + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x4" > + }, > + { > + "BriefDescription": "Counts the total number of consumed retirement slots.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "TOPDOWN_RETIRING.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003" > + }, > + { > + "BriefDescription": "Counts the total number of uops retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.ALL", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "2000003" > + }, > + { > + "BriefDescription": "Counts the number of integer divide uops retired.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.IDIV", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "2000003", > + "UMask": "0x10" > + }, > + { > + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.MS", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", > + "SampleAfterValue": "2000003", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0xc2", > + "EventName": "UOPS_RETIRED.X87", > + "PEBS": "1", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "2000003", > + "UMask": "0x2" > + } > +] > diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json > new file mode 100644 > index 000000000000..77f80d1a7cd4 > --- /dev/null > +++ b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json > @@ -0,0 +1,71 @@ > +[ > + { > + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x08", > + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0xe" > + }, > + { > + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x49", > + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0xe" > + }, > + { > + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x85", > + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x1" > + }, > + { > + "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x85", > + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "2000003", > + "Speculative": "1", > + "UMask": "0x80" > + }, > + { > + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x85", > + "EventName": "ITLB_MISSES.WALK_COMPLETED", > + "PEBScounters": "0,1,2,3,4,5", > + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", > + "SampleAfterValue": "200003", > + "Speculative": "1", > + "UMask": "0xe" > + }, > + { > + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", > + "CollectPEBSRecord": "2", > + "Counter": "0,1,2,3,4,5", > + "EventCode": "0x05", > + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", > + "PEBScounters": "0,1,2,3,4,5", > + "SampleAfterValue": "1000003", > + "Speculative": "1", > + "UMask": "0x90" > + } > +] > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/5] perf vendor events intel: Add core event list for Alderlake-N 2022-11-19 1:01 ` Ian Rogers @ 2022-11-21 2:59 ` Xing Zhengjun 0 siblings, 0 replies; 7+ messages in thread From: Xing Zhengjun @ 2022-11-21 2:59 UTC (permalink / raw) To: Ian Rogers Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On 11/19/2022 9:01 AM, Ian Rogers wrote: > On Thu, Nov 17, 2022 at 11:57 PM <zhengjun.xing@linux.intel.com> wrote: >> >> From: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> >> Alderlake-N only has E-core, it has been moved to non-hybrid code path on >> the kernel side. Add core event list for Alderlake-N, it is based on the >> ADL gracemont v1.16 JSON file. >> >> https://github.com/intel/perfmon/tree/main/ADL/events/ >> >> Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> >> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> >> --- >> .../pmu-events/arch/x86/alderlaken/cache.json | 450 ++++++++++ >> .../arch/x86/alderlaken/floating-point.json | 25 + >> .../arch/x86/alderlaken/frontend.json | 38 + >> .../arch/x86/alderlaken/memory.json | 109 +++ >> .../pmu-events/arch/x86/alderlaken/other.json | 42 + >> .../arch/x86/alderlaken/pipeline.json | 774 ++++++++++++++++++ >> .../arch/x86/alderlaken/virtual-memory.json | 71 ++ >> 7 files changed, 1509 insertions(+) >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/cache.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/frontend.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/memory.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/other.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json >> create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json >> >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json >> new file mode 100644 >> index 000000000000..a6aa87d1365b >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json >> @@ -0,0 +1,450 @@ >> +[ >> + { >> + "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x2e", >> + "EventName": "LONGEST_LAT_CACHE.MISS", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x41" > > In this event CollectPEBSRecord, Counter, PEBScounters and Speculative > are all unused in the jevents.py converter. There is a new perf json > creating tool that doesn't generate these unneeded values: > https://github.com/intel/perfmon/pull/27 > Would it not make more sense to use that to generate the AlderlakeN > data? It also fixes a number of bugs, in particular in uncore event > generation. > Ok, I will regenerate the event list with the new converter scripts. > Thanks, > Ian > >> + }, >> + { >> + "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x2e", >> + "EventName": "LONGEST_LAT_CACHE.REFERENCE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x4f" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.IFETCH", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x38" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or translation lookaside buffer (TLB) miss which hit in DRAM or MMIO (non-DRAM).", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x20" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x8" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x10" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.LOAD", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x7" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x34", >> + "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of load uops retired that hit in DRAM.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd1", >> + "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x80" >> + }, >> + { >> + "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd1", >> + "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd1", >> + "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x04", >> + "EventName": "MEM_SCHEDULER_BLOCK.ALL", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x7" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x04", >> + "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x04", >> + "EventName": "MEM_SCHEDULER_BLOCK.RSV", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x04", >> + "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of load uops retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of load uops retired.", >> + "SampleAfterValue": "200003", >> + "UMask": "0x81" >> + }, >> + { >> + "BriefDescription": "Counts the number of store uops retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.ALL_STORES", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of store uops retired.", >> + "SampleAfterValue": "200003", >> + "UMask": "0x82" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x80", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x10", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x100", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x20", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x4", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x200", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x40", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", >> + "L1_Hit_Indication": "1", >> + "MSRIndex": "0x3F6", >> + "MSRValue": "0x8", >> + "PEBS": "2", >> + "PublicDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled. If a PEBS record is generated, will populate the PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "TakenAlone": "1", >> + "UMask": "0x5" >> + }, >> + { >> + "BriefDescription": "Counts the number of retired split load uops.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x41" >> + }, >> + { >> + "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Data_LA": "1", >> + "EventCode": "0xd0", >> + "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", >> + "L1_Hit_Indication": "1", >> + "PEBS": "2", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled. If PEBS is enabled and a PEBS record is generated, will populate PEBS Latency and PEBS Data Source fields accordingly.", >> + "SampleAfterValue": "1000003", >> + "UMask": "0x6" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F803C0001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10003C0001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, but no data was forwarded.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x4003C0001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop was sent, the snoop hit, and non-modified data was forwarded.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x8003C0001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_RFO.L3_HIT", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F803C0002", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10003C0002", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.ICACHE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x20" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json >> new file mode 100644 >> index 000000000000..02eb1af8db00 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json >> @@ -0,0 +1,25 @@ >> +[ >> + { >> + "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.FP_ASSIST", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "UOPS_RETIRED.FPDIV", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "2000003", >> + "UMask": "0x8" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json >> new file mode 100644 >> index 000000000000..ed0587945a05 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json >> @@ -0,0 +1,38 @@ >> +[ >> + { >> + "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xe6", >> + "EventName": "BACLEARS.ANY", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of BACLEARS, which occur when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", >> + "SampleAfterValue": "100003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x80", >> + "EventName": "ICACHE.ACCESSES", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line or byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x3" >> + }, >> + { >> + "BriefDescription": "Counts the number of instruction cache misses.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x80", >> + "EventName": "ICACHE.MISSES", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of missed requests to the instruction cache. The event only counts new cache line accesses, so that multiple back to back fetches to the exact same cache line and byte chunk count as one. Specifically, the event counts when accesses from sequential code crosses the cache line boundary, or when a branch target is moved to a new line or to a non-sequential byte chunk of the same line.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json >> new file mode 100644 >> index 000000000000..cabf2fc8600f >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json >> @@ -0,0 +1,109 @@ >> +[ >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.ANY_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0xff" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.L1_BOUND_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0xf4" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.OTHER_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases such as pipeline conflicts, fences, etc.", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0xc0" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.PGWALK_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0xa0" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.ST_ADDR_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x84" >> + }, >> + { >> + "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F84400001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that were not supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F84400001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_RFO.L3_MISS", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F84400002", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x3F84400002", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/other.json b/tools/perf/pmu-events/arch/x86/alderlaken/other.json >> new file mode 100644 >> index 000000000000..25c7f1f47e28 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/other.json >> @@ -0,0 +1,42 @@ >> +[ >> + { >> + "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that have any type of response.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.COREWB_M.ANY_RESPONSE", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10008", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand data reads that have any type of response.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10001", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10002", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts streaming stores that have any type of response.", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xB7", >> + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", >> + "MSRIndex": "0x1a6,0x1a7", >> + "MSRValue": "0x10800", >> + "SampleAfterValue": "100003", >> + "UMask": "0x1" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json >> new file mode 100644 >> index 000000000000..f922d96e5aaa >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json >> @@ -0,0 +1,774 @@ >> +[ >> + { >> + "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.ALL_BRANCHES", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires. All branch type instructions are accounted for.", >> + "SampleAfterValue": "200003" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_CALL", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xf9" >> + }, >> + { >> + "BriefDescription": "Counts the number of retired JCC (Jump on Conditional Code) branch instructions retired, includes both taken and not taken branches.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.COND", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x7e" >> + }, >> + { >> + "BriefDescription": "Counts the number of taken JCC (Jump on Conditional Code) branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.COND_TAKEN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfe" >> + }, >> + { >> + "BriefDescription": "Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.FAR_BRANCH", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xbf" >> + }, >> + { >> + "BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.INDIRECT", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xeb" >> + }, >> + { >> + "BriefDescription": "Counts the number of near indirect CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.INDIRECT_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfb" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT_CALL", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.IND_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfb" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.JCC", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x7e" >> + }, >> + { >> + "BriefDescription": "Counts the number of near CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.NEAR_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xf9" >> + }, >> + { >> + "BriefDescription": "Counts the number of near RET branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.NEAR_RETURN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xf7" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.INDIRECT", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.NON_RETURN_IND", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xeb" >> + }, >> + { >> + "BriefDescription": "Counts the number of near relative CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.REL_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfd" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.NEAR_RETURN", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.RETURN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xf7" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_INST_RETIRED.COND_TAKEN", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc4", >> + "EventName": "BR_INST_RETIRED.TAKEN_JCC", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfe" >> + }, >> + { >> + "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of mispredicted branch instructions retired. All branch type instructions are accounted for. Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP. A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.", >> + "SampleAfterValue": "200003" >> + }, >> + { >> + "BriefDescription": "Counts the number of mispredicted JCC (Jump on Conditional Code) branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.COND", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x7e" >> + }, >> + { >> + "BriefDescription": "Counts the number of mispredicted taken JCC (Jump on Conditional Code) branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.COND_TAKEN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfe" >> + }, >> + { >> + "BriefDescription": "Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.INDIRECT", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xeb" >> + }, >> + { >> + "BriefDescription": "Counts the number of mispredicted near indirect CALL branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfb" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT_CALL", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.IND_CALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfb" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.JCC", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0x7e" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.INDIRECT", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xeb" >> + }, >> + { >> + "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.RETURN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xf7" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event BR_MISP_RETIRED.COND_TAKEN", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0xc5", >> + "EventName": "BR_MISP_RETIRED.TAKEN_JCC", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "200003", >> + "UMask": "0xfe" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", >> + "CollectPEBSRecord": "2", >> + "Counter": "Fixed counter 1", >> + "EventName": "CPU_CLK_UNHALTED.CORE", >> + "PEBScounters": "33", >> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted core clock cycles.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x3c", >> + "EventName": "CPU_CLK_UNHALTED.CORE_P", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency. (Fixed event)", >> + "CollectPEBSRecord": "2", >> + "Counter": "Fixed counter 2", >> + "EventName": "CPU_CLK_UNHALTED.REF_TSC", >> + "PEBScounters": "34", >> + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0x3" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x3c", >> + "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted core clock cycles. (Fixed event)", >> + "CollectPEBSRecord": "2", >> + "Counter": "Fixed counter 1", >> + "EventName": "CPU_CLK_UNHALTED.THREAD", >> + "PEBScounters": "33", >> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of unhalted core clock cycles.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x3c", >> + "EventName": "CPU_CLK_UNHALTED.THREAD_P", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1" >> + }, >> + { >> + "BriefDescription": "Counts the total number of instructions retired. (Fixed event)", >> + "CollectPEBSRecord": "2", >> + "Counter": "Fixed counter 0", >> + "EventName": "INST_RETIRED.ANY", >> + "PEBS": "1", >> + "PEBScounters": "32", >> + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0.", >> + "SampleAfterValue": "2000003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the total number of instructions retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc0", >> + "EventName": "INST_RETIRED.ANY_P", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of instructions that retired. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. This event continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses a programmable general purpose performance counter.", >> + "SampleAfterValue": "2000003" >> + }, >> + { >> + "BriefDescription": "This event is deprecated. Refer to new event LD_BLOCKS.ADDRESS_ALIAS", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "Deprecated": "1", >> + "EventCode": "0x03", >> + "EventName": "LD_BLOCKS.4K_ALIAS", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x03", >> + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x03", >> + "EventName": "LD_BLOCKS.DATA_UNKNOWN", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.DISAMBIGUATION", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x8" >> + }, >> + { >> + "BriefDescription": "Counts the number of machines clears due to memory renaming.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.MRN_NUKE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x80" >> + }, >> + { >> + "BriefDescription": "Counts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A page fault occurs when either the page is not present, or an access violation occurs.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.PAGE_FAULT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x20" >> + }, >> + { >> + "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine with the use of microcode due to SMC, MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_TRAP.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.SLOW", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x6f" >> + }, >> + { >> + "BriefDescription": "Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc3", >> + "EventName": "MACHINE_CLEARS.SMC", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "20003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x75", >> + "EventName": "SERIALIZATION.NON_C01_MS_SCB", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x73", >> + "EventName": "TOPDOWN_BAD_SPECULATION.ALL", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ) even if an FE_bound event occurs during this period. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to fast nukes such as memory ordering and memory disambiguation machine clears.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x73", >> + "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x73", >> + "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x3" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to branch mispredicts.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x73", >> + "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x73", >> + "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to backend stalls.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.ALL", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to certain allocation restrictions.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x8" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.REGISTER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x20" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x40" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x74", >> + "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x10" >> + }, >> + { >> + "BriefDescription": "Counts the total number of issue slots every cycle that were not consumed by the backend due to frontend stalls.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.ALL", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x2" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x40" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to the microcode sequencer (MS).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.CISC", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stalls.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.DECODE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x8" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x8d" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to a latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x72" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB misses.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.ITLB", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x10" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to other common frontend stalls not categorized.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.OTHER", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x80" >> + }, >> + { >> + "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to wrong predecodes.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x71", >> + "EventName": "TOPDOWN_FE_BOUND.PREDECODE", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x4" >> + }, >> + { >> + "BriefDescription": "Counts the total number of consumed retirement slots.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "TOPDOWN_RETIRING.ALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003" >> + }, >> + { >> + "BriefDescription": "Counts the total number of uops retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "UOPS_RETIRED.ALL", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "2000003" >> + }, >> + { >> + "BriefDescription": "Counts the number of integer divide uops retired.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "UOPS_RETIRED.IDIV", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "2000003", >> + "UMask": "0x10" >> + }, >> + { >> + "BriefDescription": "Counts the number of uops that are from complex flows issued by the micro-sequencer (MS).", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "UOPS_RETIRED.MS", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of uops that are from complex flows issued by the Microcode Sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", >> + "SampleAfterValue": "2000003", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of x87 uops retired, includes those in MS flows.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0xc2", >> + "EventName": "UOPS_RETIRED.X87", >> + "PEBS": "1", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "2000003", >> + "UMask": "0x2" >> + } >> +] >> diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json >> new file mode 100644 >> index 000000000000..77f80d1a7cd4 >> --- /dev/null >> +++ b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json >> @@ -0,0 +1,71 @@ >> +[ >> + { >> + "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x08", >> + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0xe" >> + }, >> + { >> + "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x49", >> + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0xe" >> + }, >> + { >> + "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x85", >> + "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x1" >> + }, >> + { >> + "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x85", >> + "EventName": "ITLB_MISSES.PDE_CACHE_MISS", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "2000003", >> + "Speculative": "1", >> + "UMask": "0x80" >> + }, >> + { >> + "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x85", >> + "EventName": "ITLB_MISSES.WALK_COMPLETED", >> + "PEBScounters": "0,1,2,3,4,5", >> + "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.", >> + "SampleAfterValue": "200003", >> + "Speculative": "1", >> + "UMask": "0xe" >> + }, >> + { >> + "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.", >> + "CollectPEBSRecord": "2", >> + "Counter": "0,1,2,3,4,5", >> + "EventCode": "0x05", >> + "EventName": "LD_HEAD.DTLB_MISS_AT_RET", >> + "PEBScounters": "0,1,2,3,4,5", >> + "SampleAfterValue": "1000003", >> + "Speculative": "1", >> + "UMask": "0x90" >> + } >> +] >> -- >> 2.25.1 >> -- Zhengjun Xing ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/5] perf vendor events intel: Add uncore event list for Alderlake-N 2022-11-18 7:56 [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N zhengjun.xing 2022-11-18 7:56 ` [PATCH 2/5] perf vendor events intel: Add core event list " zhengjun.xing @ 2022-11-18 7:57 ` zhengjun.xing 2022-11-18 7:57 ` [PATCH 4/5] perf vendor events intel: Add metrics " zhengjun.xing 2022-11-19 1:11 ` [PATCH 1/5] perf vendor events: Add the cpuid " Ian Rogers 3 siblings, 0 replies; 7+ messages in thread From: zhengjun.xing @ 2022-11-18 7:57 UTC (permalink / raw) To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang, zhengjun.xing From: Zhengjun Xing <zhengjun.xing@linux.intel.com> Add JSON uncore events for Alderlake-N Based on JSON list v1.16: https://github.com/intel/perfmon/tree/main/ADL/events/ Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- .../arch/x86/alderlaken/uncore-memory.json | 222 ++++++++++++++++++ .../arch/x86/alderlaken/uncore-other.json | 87 +++++++ 2 files changed, 309 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json new file mode 100644 index 000000000000..d82d6f62a6fb --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json @@ -0,0 +1,222 @@ +[ + { + "BriefDescription": "Number of clocks", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x02", + "EventName": "UNC_M_VC0_REQUESTS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x03", + "EventName": "UNC_M_VC0_REQUESTS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x04", + "EventName": "UNC_M_VC1_REQUESTS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x05", + "EventName": "UNC_M_VC1_REQUESTS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Incoming read prefetch request from IA", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x0A", + "EventName": "UNC_M_PREFETCH_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Hot state", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x19", + "EventName": "UNC_M_DRAM_THERMAL_HOT", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Any Rank at Warm state", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1A", + "EventName": "UNC_M_DRAM_THERMAL_WARM", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Hit", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1C", + "EventName": "UNC_M_DRAM_PAGE_HIT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Empty", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1D", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming read request page status is Page Miss", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1E", + "EventName": "UNC_M_DRAM_PAGE_MISS_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Hit", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x1F", + "EventName": "UNC_M_DRAM_PAGE_HIT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Empty", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x20", + "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "incoming write request page status is Page Miss", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x21", + "EventName": "UNC_M_DRAM_PAGE_MISS_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x22", + "EventName": "UNC_M_CAS_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x23", + "EventName": "UNC_M_CAS_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x24", + "EventName": "UNC_M_ACT_COUNT_RD", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x25", + "EventName": "UNC_M_ACT_COUNT_WR", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x26", + "EventName": "UNC_M_ACT_COUNT_TOTAL", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command sent to DRAM for a read/write request", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x27", + "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration", + "Counter": "0,1,2,3,4", + "CounterType": "PGMABLE", + "EventCode": "0x28", + "EventName": "UNC_M_PRE_COUNT_IDLE", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)", + "Counter": "3", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", + "Counter": "1", + "CounterType": "FREERUN", + "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + }, + { + "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM", + "Counter": "4", + "CounterType": "FREERUN", + "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", + "PerPkg": "1", + "Unit": "iMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json new file mode 100644 index 000000000000..8a31b0e0a1b7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json @@ -0,0 +1,87 @@ +[ + { + "BriefDescription": "Counts the number of coherent and in-coherent requests initiated by IA cores, processor graphic units, or LLC", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_ARB_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of requests allocated in Coherency Tracker", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x84", + "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles", + "Counter": "Fixed", + "CounterType": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "CLOCK" + }, + { + "BriefDescription": "Each cycle counts number of all outgoing valid entries in ReqTrk. Such entry is defined as valid from its allocation in ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic", + "CounterType": "PGMABLE", + "EventCode": "0x80", + "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_REQUESTS.RD", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "This event is deprecated. Refer to new event UNC_ARB_DAT_OCCUPANCY.ALL", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of any coherent request at memory controller that were issued by any core", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "PerPkg": "1", + "UMask": "0x01", + "Unit": "ARB" + }, + { + "BriefDescription": "Number of coherent read requests sent to memory controller that were issued by any core", + "Counter": "0,1", + "CounterType": "PGMABLE", + "EventCode": "0x81", + "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "ARB" + }, + { + "BriefDescription": "Each cycle counts number of coherent reads pending on data return from memory controller that were issued by any core", + "CounterType": "PGMABLE", + "EventCode": "0x85", + "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "PerPkg": "1", + "UMask": "0x02", + "Unit": "ARB" + } +] -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 4/5] perf vendor events intel: Add metrics for Alderlake-N 2022-11-18 7:56 [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N zhengjun.xing 2022-11-18 7:56 ` [PATCH 2/5] perf vendor events intel: Add core event list " zhengjun.xing 2022-11-18 7:57 ` [PATCH 3/5] perf vendor events intel: Add uncore " zhengjun.xing @ 2022-11-18 7:57 ` zhengjun.xing 2022-11-19 1:11 ` [PATCH 1/5] perf vendor events: Add the cpuid " Ian Rogers 3 siblings, 0 replies; 7+ messages in thread From: zhengjun.xing @ 2022-11-18 7:57 UTC (permalink / raw) To: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung Cc: linux-kernel, linux-perf-users, irogers, ak, kan.liang, zhengjun.xing From: Zhengjun Xing <zhengjun.xing@linux.intel.com> Add JSON metrics for Alderlake-N to perf. It only included E-core metrics. E-core metrics based on E-core TMA v2.2 (E-core_TMA_Metrics.csv) It is downloaded from: https://github.com/intel/perfmon/ Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> Reviewed-by: Kan Liang <kan.liang@linux.intel.com> --- .../arch/x86/alderlaken/adln-metrics.json | 573 ++++++++++++++++++ 1 file changed, 573 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json new file mode 100644 index 000000000000..acafdc7cef2d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -0,0 +1,573 @@ +[ + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS", + "MetricGroup": "TopdownL1", + "MetricName": "tma_frontend_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / SLOTS", + "MetricGroup": "TopdownL2;tma_frontend_bound_group", + "MetricName": "tma_frontend_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_latency_group", + "MetricName": "tma_icache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_latency_group", + "MetricName": "tma_itlb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_latency_group", + "MetricName": "tma_branch_detect", + "PublicDescription": "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was corrected by a later branch predictor in the frontend. Includes BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which occurs when the Branch Target Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_latency_group", + "MetricName": "tma_branch_resteer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to frontend bandwidth restrictions due to decode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / SLOTS", + "MetricGroup": "TopdownL2;tma_frontend_bound_group", + "MetricName": "tma_frontend_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", + "MetricName": "tma_cisc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", + "MetricName": "tma_decode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", + "MetricName": "tma_predecode", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not delivered by the frontend due to other common frontend stalls not categorized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / SLOTS", + "MetricGroup": "TopdownL3;tma_frontend_bandwidth_group", + "MetricName": "tma_other_fb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear", + "MetricExpr": "(SLOTS - (TOPDOWN_FE_BOUND.ALL + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / SLOTS", + "MetricGroup": "TopdownL1", + "MetricName": "tma_bad_speculation", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window including relevant microcode flows and while uops are not yet available in the instruction queue (IQ). Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to branch mispredicts.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / SLOTS", + "MetricGroup": "TopdownL2;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a machine clear (nuke) of any kind including memory ordering and memory disambiguation.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / SLOTS", + "MetricGroup": "TopdownL2;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear (slow nuke).", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / SLOTS", + "MetricGroup": "TopdownL3;tma_machine_clears_group", + "MetricName": "tma_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to SMC. ", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_nuke_group", + "MetricName": "tma_smc", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory ordering. ", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_nuke_group", + "MetricName": "tma_memory_ordering", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to FP assists. ", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_nuke_group", + "MetricName": "tma_fp_assist", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to memory disambiguation. ", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_nuke_group", + "MetricName": "tma_disambiguation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of machine clears relative to the number of nuke slots due to page faults. ", + "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLEARS.SLOW)", + "MetricGroup": "TopdownL4;tma_nuke_group", + "MetricName": "tma_page_fault", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to a machine clear classified as a fast nuke due to memory ordering, memory disambiguation and memory renaming.", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / SLOTS", + "MetricGroup": "TopdownL3;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL / SLOTS", + "MetricGroup": "TopdownL1", + "MetricName": "tma_backend_bound", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. The rest of these subevents count backend stalls, in cycles, due to an outstanding request which is memory bound vs core bound. The subevents are not slot based events and therefore can not be precisely added or subtracted from the Backend_Bound_Aux subevents which are slot based.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bound stalls that are core execution bound and not attributed to outstanding demand load or store stalls. ", + "MetricExpr": "max(0, tma_backend_bound - tma_load_store_bound)", + "MetricGroup": "TopdownL2;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to stores or loads. ", + "MetricExpr": "min((TOPDOWN_BE_BOUND.ALL / SLOTS), (LD_HEAD.ANY_AT_RET / CLKS) + tma_store_bound)", + "MetricGroup": "TopdownL2;tma_backend_bound_group", + "MetricName": "tma_load_store_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to store buffer full.", + "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_store_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a load block.", + "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / CLKS", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a store forward block.", + "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_store_fwd", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a first level TLB miss.", + "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_stlb_hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a second level TLB miss requiring a page walk.", + "MetricExpr": "LD_HEAD.PGWALK_AT_RET / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_stlb_miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest load of the load buffer is stalled at retirement due to a number of other load blocks.", + "MetricExpr": "LD_HEAD.OTHER_AT_RET / CLKS", + "MetricGroup": "TopdownL4;tma_l1_bound_group", + "MetricName": "tma_other_l1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 Cache.", + "MetricExpr": "(MEM_BOUND_STALLS.LOAD_L2_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD)", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_l2_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", + "MetricExpr": "(MEM_BOUND_STALLS.LOAD_LLC_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD)", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_l3_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "MetricExpr": "(MEM_BOUND_STALLS.LOAD_DRAM_HIT / CLKS) - (MEM_BOUND_STALLS_AT_RET_CORRECTION * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD)", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_dram_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-DRAM) but could not be correctly attributed or cycles in which the load miss is waiting on a request buffer.", + "MetricExpr": "max(0, tma_load_store_bound - (tma_store_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", + "MetricGroup": "TopdownL3;tma_load_store_bound_group", + "MetricName": "tma_other_load_store", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL1", + "MetricName": "tma_backend_bound_aux", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that UOPS must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. All of these subevents count backend stalls, in slots, due to a resource limitation. These are not cycle based events and therefore can not be precisely added or subtracted from the Backend_Bound subevents which are cycle based. These subevents are supplementary to Backend_Bound and can be used to analyze results from a resource perspective at allocation. ", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls", + "MetricExpr": "tma_backend_bound", + "MetricGroup": "TopdownL2;tma_backend_bound_aux_group", + "MetricName": "tma_resource_bound", + "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend due to backend stalls. Note that uops must be available for consumption in order for this event to count. If a uop is not available (IQ is empty), this event will not count. ", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to memory reservation stalls in which a scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to store buffer full", + "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_BLOCK.ALL)", + "MetricGroup": "TopdownL4;tma_mem_scheduler_group", + "MetricName": "tma_st_buffer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to load buffer full", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_mem_scheduler_group", + "MetricName": "tma_ld_buffer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles, relative to the number of mem_scheduler slots, in which uops are blocked due to RSV full relative ", + "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_SCHEDULER_BLOCK.ALL", + "MetricGroup": "TopdownL4;tma_mem_scheduler_group", + "MetricName": "tma_rsv", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to IEC or FPC RAT stalls, which can be due to FIQ or IEC reservation stalls in which the integer, floating point or SIMD scheduler is not able to accept uops.", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the physical register file unable to accept an entry (marble stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_register", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to the reorder buffer being full (ROB stalls).", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to certain allocation restrictions.", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_alloc_restriction", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to scoreboards from the instruction queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / SLOTS", + "MetricGroup": "TopdownL3;tma_resource_bound_group", + "MetricName": "tma_serialization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the numer of issue slots that result in retirement slots. ", + "MetricExpr": "TOPDOWN_RETIRING.ALL / SLOTS", + "MetricGroup": "TopdownL1", + "MetricName": "tma_retiring", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of uops that are not from the microsequencer. ", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / SLOTS", + "MetricGroup": "TopdownL2;tma_retiring_group", + "MetricName": "tma_base", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of floating point operations per uop with all default weighting.", + "MetricExpr": "UOPS_RETIRED.FPDIV / SLOTS", + "MetricGroup": "TopdownL3;tma_base_group", + "MetricName": "tma_fp_uops", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of uops retired excluding ms and fp div uops.", + "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETIRED.FPDIV) / SLOTS", + "MetricGroup": "TopdownL3;tma_base_group", + "MetricName": "tma_other_ret", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS)", + "MetricExpr": "UOPS_RETIRED.MS / SLOTS", + "MetricGroup": "TopdownL2;tma_retiring_group", + "MetricName": "tma_ms_uops", + "PublicDescription": "Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS). This includes uops from flows due to complex instructions, faults, assists, and inserted flows.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE", + "MetricName": "CLKS" + }, + { + "BriefDescription": "", + "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", + "MetricName": "CLKS_P" + }, + { + "BriefDescription": "", + "MetricExpr": "5 * CLKS", + "MetricName": "SLOTS" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / CLKS", + "MetricName": "IPC" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "CLKS / INST_RETIRED.ANY", + "MetricName": "CPI" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", + "MetricName": "UPI" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "Store_Fwd_Blocks" + }, + { + "BriefDescription": "Percentage of total non-speculative loads with a address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "Address_Alias_Blocks" + }, + { + "BriefDescription": "Percentage of total non-speculative loads that are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "Load_Splits" + }, + { + "BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "IpBranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", + "MetricName": "IpCall" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "IpLoad" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricName": "IpStore" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricName": "IpMispredict" + }, + { + "BriefDescription": "Instructions per Far Branch", + "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)", + "MetricName": "IpFarBranch" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "Branch_Mispredict_Ratio" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unknown branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricName": "Branch_Mispredict_to_Unknown_Branch_Ratio" + }, + { + "BriefDescription": "Percentage of all uops which are ucode ops", + "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricName": "Microcode_Uop_Ratio" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricName": "FPDiv_Uop_Ratio" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricName": "IDiv_Uop_Ratio" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricName": "X87_Uop_Ratio" + }, + { + "BriefDescription": "Average Frequency Utilization relative nominal frequency", + "MetricExpr": "CLKS / CPU_CLK_UNHALTED.REF_TSC", + "MetricName": "Turbo_Utilization" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE", + "MetricName": "Kernel_Utilization" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", + "MetricName": "CPU_Utilization" + }, + { + "BriefDescription": "Cycle cost per L2 hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRED.L2_HIT", + "MetricName": "Cycles_per_Demand_Load_L2_Hit" + }, + { + "BriefDescription": "Cycle cost per LLC hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIRED.L3_HIT", + "MetricName": "Cycles_per_Demand_Load_L3_Hit" + }, + { + "BriefDescription": "Cycle cost per DRAM hit", + "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETIRED.DRAM_HIT", + "MetricName": "Cycles_per_Demand_Load_DRAM_Hit" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / (MEM_BOUND_STALLS.IFETCH)", + "MetricName": "Inst_Miss_Cost_L2Hit_Percent" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / (MEM_BOUND_STALLS.IFETCH)", + "MetricName": "Inst_Miss_Cost_L3Hit_Percent" + }, + { + "BriefDescription": "Percent of instruction miss cost that hit in DRAM", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / (MEM_BOUND_STALLS.IFETCH)", + "MetricName": "Inst_Miss_Cost_DRAMHit_Percent" + }, + { + "BriefDescription": "load ops retired per 1000 instruction", + "MetricExpr": "1000 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricName": "MemLoadPKI" + }, + { + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency" + }, + { + "BriefDescription": "C7 residency percent per core", + "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Core_Residency" + }, + { + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency" + }, + { + "BriefDescription": "C3 residency percent per package", + "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C3_Pkg_Residency" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency" + }, + { + "BriefDescription": "C7 residency percent per package", + "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C7_Pkg_Residency" + }, + { + "BriefDescription": "C8 residency percent per package", + "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C8_Pkg_Residency" + }, + { + "BriefDescription": "C9 residency percent per package", + "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C9_Pkg_Residency" + }, + { + "BriefDescription": "C10 residency percent per package", + "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100", + "MetricGroup": "Power", + "MetricName": "C10_Pkg_Residency" + } +] -- 2.25.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N 2022-11-18 7:56 [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N zhengjun.xing ` (2 preceding siblings ...) 2022-11-18 7:57 ` [PATCH 4/5] perf vendor events intel: Add metrics " zhengjun.xing @ 2022-11-19 1:11 ` Ian Rogers 3 siblings, 0 replies; 7+ messages in thread From: Ian Rogers @ 2022-11-19 1:11 UTC (permalink / raw) To: zhengjun.xing Cc: acme, peterz, mingo, alexander.shishkin, jolsa, namhyung, linux-kernel, linux-perf-users, ak, kan.liang On Thu, Nov 17, 2022 at 11:56 PM <zhengjun.xing@linux.intel.com> wrote: > > From: Zhengjun Xing <zhengjun.xing@linux.intel.com> > > Alderlake-N only has E-core, it has been moved to non-hybrid code path on > the kernel side, add the cpuid for Alderlake-N separately. Both events for > Alderlake and Alderlake-N are based on JSON file v1.16. The update to 1.16 is true at the end of the patch series rather than the beginning. It makes more sense to bump the version in the same change that updates the json otherwise reverting the json changes leaves the version number in place. Thanks, Ian > Signed-off-by: Zhengjun Xing <zhengjun.xing@linux.intel.com> > Reviewed-by: Kan Liang <kan.liang@linux.intel.com> > --- > tools/perf/pmu-events/arch/x86/mapfile.csv | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv > index 5e609b876790..df47462a125f 100644 > --- a/tools/perf/pmu-events/arch/x86/mapfile.csv > +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv > @@ -1,5 +1,6 @@ > Family-model,Version,Filename,EventType > -GenuineIntel-6-(97|9A|B7|BA|BE|BF),v1.15,alderlake,core > +GenuineIntel-6-(97|9A|B7|BA|BF),v1.16,alderlake,core > +GenuineIntel-6-BE,v1.16,alderlaken,core > GenuineIntel-6-(1C|26|27|35|36),v4,bonnell,core > GenuineIntel-6-(3D|47),v26,broadwell,core > GenuineIntel-6-56,v23,broadwellde,core > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-11-21 2:59 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-11-18 7:56 [PATCH 1/5] perf vendor events: Add the cpuid for Alderlake-N zhengjun.xing 2022-11-18 7:56 ` [PATCH 2/5] perf vendor events intel: Add core event list " zhengjun.xing 2022-11-19 1:01 ` Ian Rogers 2022-11-21 2:59 ` Xing Zhengjun 2022-11-18 7:57 ` [PATCH 3/5] perf vendor events intel: Add uncore " zhengjun.xing 2022-11-18 7:57 ` [PATCH 4/5] perf vendor events intel: Add metrics " zhengjun.xing 2022-11-19 1:11 ` [PATCH 1/5] perf vendor events: Add the cpuid " Ian Rogers
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