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X-CSE-ConnectionGUID: 0gHgzWfaSrO8TjTOw3x+dQ== X-CSE-MsgGUID: fLTy8AovTFufYYOrRSXSlQ== X-IronPort-AV: E=McAfee;i="6600,9927,11042"; a="8997120" X-IronPort-AV: E=Sophos;i="6.07,198,1708416000"; d="scan'208";a="8997120" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by fmvoesa110.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2024 19:29:25 -0700 X-CSE-ConnectionGUID: PDLcfHYZR3WcpCn+Zk2lnw== X-CSE-MsgGUID: PYzeBqfvTn+ujWOP8/+T5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,198,1708416000"; d="scan'208";a="21829776" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.225.92]) ([10.124.225.92]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2024 19:29:21 -0700 Message-ID: <1e6d458c-ce9e-4ef2-9985-359c7b708bd3@linux.intel.com> Date: Sat, 13 Apr 2024 10:29:18 +0800 Precedence: bulk X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 23/41] KVM: x86/pmu: Implement the save/restore of PMU state for Intel CPU To: Sean Christopherson , Xiong Zhang Cc: pbonzini@redhat.com, peterz@infradead.org, mizhang@google.com, kan.liang@intel.com, zhenyuw@linux.intel.com, jmattson@google.com, kvm@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, zhiyuan.lv@intel.com, eranian@google.com, irogers@google.com, samantha.alt@intel.com, like.xu.linux@gmail.com, chao.gao@intel.com References: <20240126085444.324918-1-xiong.y.zhang@linux.intel.com> <20240126085444.324918-24-xiong.y.zhang@linux.intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 4/12/2024 5:26 AM, Sean Christopherson wrote: > On Fri, Jan 26, 2024, Xiong Zhang wrote: >> static void intel_save_pmu_context(struct kvm_vcpu *vcpu) >> { >> + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); >> + struct kvm_pmc *pmc; >> + u32 i; >> + >> + if (pmu->version != 2) { >> + pr_warn("only PerfMon v2 is supported for passthrough PMU"); >> + return; >> + } >> + >> + /* Global ctrl register is already saved at VM-exit. */ >> + rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, pmu->global_status); >> + /* Clear hardware MSR_CORE_PERF_GLOBAL_STATUS MSR, if non-zero. */ >> + if (pmu->global_status) >> + wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, pmu->global_status); >> + >> + for (i = 0; i < pmu->nr_arch_gp_counters; i++) { >> + pmc = &pmu->gp_counters[i]; >> + rdpmcl(i, pmc->counter); >> + rdmsrl(i + MSR_ARCH_PERFMON_EVENTSEL0, pmc->eventsel); >> + /* >> + * Clear hardware PERFMON_EVENTSELx and its counter to avoid >> + * leakage and also avoid this guest GP counter get accidentally >> + * enabled during host running when host enable global ctrl. >> + */ >> + if (pmc->eventsel) >> + wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0); >> + if (pmc->counter) >> + wrmsrl(MSR_IA32_PMC0 + i, 0); >> + } >> + >> + rdmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, pmu->fixed_ctr_ctrl); >> + /* >> + * Clear hardware FIXED_CTR_CTRL MSR to avoid information leakage and >> + * also avoid these guest fixed counters get accidentially enabled >> + * during host running when host enable global ctrl. >> + */ >> + if (pmu->fixed_ctr_ctrl) >> + wrmsrl(MSR_CORE_PERF_FIXED_CTR_CTRL, 0); >> + for (i = 0; i < pmu->nr_arch_fixed_counters; i++) { >> + pmc = &pmu->fixed_counters[i]; >> + rdpmcl(INTEL_PMC_FIXED_RDPMC_BASE | i, pmc->counter); >> + if (pmc->counter) >> + wrmsrl(MSR_CORE_PERF_FIXED_CTR0 + i, 0); >> + } > For the next RFC, please make that it includes AMD support. Mostly because I'm > pretty all of this code can be in common x86. The fixed counters are ugly, > but pmu->nr_arch_fixed_counters is guaranteed to '0' on AMD, so it's _just_ ugly, > i.e. not functionally problematic. Sure. I believe Mingwei would integrate AMD supporting patches in next version. Yeah, I agree there could be a part of code which can be put into common x86/pmu, but there are still some vendor specific code, we still keep an vendor specific callback.