From: Andi Kleen <andi@firstfloor.org>
To: Manuel Selva <selva.manuel@gmail.com>
Cc: Andi Kleen <andi@firstfloor.org>,
Andreas Hollmann <hollmann@in.tum.de>,
Manuel Selva <manuel.selva@insa-lyon.fr>,
linux-perf-users@vger.kernel.org
Subject: Re: Link between Intel documentation events and perf list events
Date: Wed, 3 Jul 2013 15:28:44 +0200 [thread overview]
Message-ID: <20130703132844.GJ6123@two.firstfloor.org> (raw)
In-Reply-To: <51D3E9A5.2010804@gmail.com>
> __asm__("movl $0xa, %%eax" : ); // Moves 0xA in EAX: CPUID input param to get performance monitoring info
> __asm__("cpuid" : );
> __asm__("movl %%eax, %0" :"=r"(resultEax) : :);
> __asm__("movl %%ebx, %0" :"=r"(resultEbx) : :);
> __asm__("movl %%edx, %0" :"=r"(resultEdx) : :);
This is not a correct way to write gcc inline assembler, you cannot
assume that registers stay valid between assembler statements.
The easiest way is to use the macros from cpuid.h.
Here's a valid test program. Various Intel CPUs report REF_TSC (2) not
there, but it's really there, just not quite following the
descriptions. Other than that the architectural events are generally
available.
#include <cpuid.h>
#include <stdio.h>
int main()
{
unsigned a, b, c, d;
/* check __get_cpuid_max here */
__cpuid(10, a, b, c, d);
printf("eax: %x ebx %x ecx %x edx %x\n", a, b, c, d);
int i;
for (i = 0; i < 10; i++)
if (b & (1 << i))
printf("event %d not supported\n", i);
return 0;
}
-Andi
next prev parent reply other threads:[~2013-07-03 13:28 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-01 16:10 Link between Intel documentation events and perf list events Manuel Selva
2013-07-02 3:55 ` Andi Kleen
2013-07-02 7:53 ` Manuel Selva
2013-07-02 12:39 ` Andreas Hollmann
2013-07-02 13:33 ` Manuel Selva
2013-07-02 14:49 ` Andi Kleen
2013-07-03 9:06 ` Manuel Selva
2013-07-03 13:28 ` Andi Kleen [this message]
2013-07-03 14:02 ` Manuel Selva
[not found] ` <51D28568.8070904@insa-lyon.fr>
2013-07-02 14:41 ` Andi Kleen
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