From mboxrd@z Thu Jan  1 00:00:00 1970
From: Andi Kleen <andi@firstfloor.org>
Subject: Re: Link between Intel documentation events and perf list events
Date: Wed, 3 Jul 2013 15:28:44 +0200
Message-ID: <20130703132844.GJ6123@two.firstfloor.org>
References: <51D1AA04.7060403@insa-lyon.fr>
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To: Manuel Selva <selva.manuel@gmail.com>
Cc: Andi Kleen <andi@firstfloor.org>, Andreas Hollmann <hollmann@in.tum.de>, Manuel Selva <manuel.selva@insa-lyon.fr>, linux-perf-users@vger.kernel.org

>     __asm__("movl $0xa, %%eax" : ); // Moves 0xA in EAX: CPUID input param to get performance monitoring info
>     __asm__("cpuid" : );
>     __asm__("movl %%eax, %0" :"=r"(resultEax) : :);
>     __asm__("movl %%ebx, %0" :"=r"(resultEbx) : :);
>     __asm__("movl %%edx, %0" :"=r"(resultEdx) : :);

This is not a correct way to write gcc inline assembler, you cannot 
assume that registers stay valid between assembler statements.

The easiest way is to use the macros from cpuid.h.

Here's a valid test program. Various Intel CPUs report REF_TSC (2) not
there, but it's really there, just not quite following the
descriptions. Other than that the architectural events are generally
available.

#include <cpuid.h>
#include <stdio.h>
int main()
{
	unsigned a, b, c, d;
	/* check __get_cpuid_max here */
	__cpuid(10, a, b, c, d);
	printf("eax: %x ebx %x ecx %x edx %x\n", a, b, c, d);
	int i;
	for (i = 0; i < 10; i++) 
		if (b & (1 << i))
			printf("event %d not supported\n", i);
	return 0;
}


-Andi