From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Ingo Molnar <mingo@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Andi Kleen <ak@linux.intel.com>,
Arnaldo Carvalho de Melo <acme@redhat.com>
Subject: [PATCH 27/43] perf vendor events intel: Update IvyTown files to V20
Date: Tue, 23 Jan 2018 10:12:35 -0300 [thread overview]
Message-ID: <20180123131251.28197-28-acme@kernel.org> (raw)
In-Reply-To: <20180123131251.28197-1-acme@kernel.org>
From: Andi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.com
Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/x86/ivytown/cache.json | 456 +++++++++++++++++++++
tools/perf/pmu-events/arch/x86/ivytown/memory.json | 348 ++++++++++++++++
2 files changed, 804 insertions(+)
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
index d8cc93b3a04c..6dad3ad6b102 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json
@@ -800,5 +800,461 @@
"SampleAfterValue": "100003",
"BriefDescription": "Split locks in SQ",
"CounterHTOff": "0,1,2,3,4,5,6,7"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c0091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c0091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c0091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0090",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all prefetch data reads that hit the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c0090",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0090",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c0090",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c0090",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c03f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c03f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c03f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c03f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c03f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the LLC and sibling core snoop returned a clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10008",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all writebacks from the core to the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand data reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c0001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c0001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c0001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoop returned a clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x803c8000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts L2 hints sent to LLC to keep a line from being evicted out of the core caches",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x23ffc08000",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0040",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c0010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c0010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c0010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0200",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3f803c0080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x4003c0080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10003c0080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_CORE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x1003c0080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x2003c0080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10400",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x10800",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts non-temporal stores",
+ "CounterHTOff": "0,1,2,3"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
index 4ec94df8d70b..3a7b86af8816 100644
--- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json
+++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json
@@ -151,5 +151,353 @@
"PRECISE_STORE": "1",
"TakenAlone": "1",
"CounterHTOff": "3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc00244",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67f800244",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data returned from remote dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x87f800244",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand & prefetch code reads that miss the LLC and the data forwarded from remote cache",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20091",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand & prefetch data reads that hits the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc203f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x6004003f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data returned from local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x87f8203f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC and the data forwarded from remote cache",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x107fc003f7",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that miss the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x600400004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67f800004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x87f820004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x107fc00004",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67fc00001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x600400001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67f800001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x87f820001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x107fc00001",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x107fc20002",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all demand data writes (RFOs) that miss the LLC and the data is found in M state in remote cache and forwarded from there.",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20040",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67fc00010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x600400010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x67f800010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x87f820010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x107fc00010",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20200",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC",
+ "CounterHTOff": "0,1,2,3"
+ },
+ {
+ "EventCode": "0xB7, 0xBB",
+ "MSRValue": "0x3fffc20080",
+ "Counter": "0,1,2,3",
+ "UMask": "0x1",
+ "Offcore": "1",
+ "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE",
+ "MSRIndex": "0x1a6,0x1a7",
+ "SampleAfterValue": "100003",
+ "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that miss in the LLC",
+ "CounterHTOff": "0,1,2,3"
}
]
\ No newline at end of file
--
2.14.3
next prev parent reply other threads:[~2018-01-23 13:12 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-23 13:12 [GIT PULL 00/43] perf/core improvements and changes Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 01/43] perf intel-pt/bts: Do not swap when synthesizing samples Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 02/43] perf evsel: Ensure reserved member of PERF_SAMPLE_CPU is zero in perf_event__synthesize_sample() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 03/43] perf tools: Get rid of unused 'swapped' parameter from perf_event__synthesize_sample() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 04/43] perf tools: Use ui__error() for reporting --fields errors Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 05/43] perf bpf: Don't warn about unavailability of builtin clang, just fallback Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 06/43] perf tools: Move conditional O_CLOEXEC to util.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 07/43] perf symbols: Using O_CLOEXEC in do_open Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 08/43] perf report: Fix regression when decoding intel_pt traces Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 09/43] perf build: Display EXTRA features for VF=1 build Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 10/43] tools include arch: Grab a copy of errno.h for arch's supported by perf Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 11/43] tools include asm-generic: Grab errno.h and errno-base.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 12/43] perf util: Introduce architecture specific errno/name mapping Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 13/43] perf trace: Obtain errno strings by using arch_syscalls__strerrno() Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 14/43] perf trace: Remove audit-libs dependency if syscall tables are present Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 15/43] perf vendor events intel: Update Broadwell events to V22 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 16/43] perf vendor events intel: Update BroadwellX events to V13 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 17/43] perf vendor events intel: Update Goldmont events to V12 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 18/43] perf vendor events intel: Update Haswell events to V27 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 19/43] perf vendor events intel: Update HaswellX events to V19 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 20/43] perf vendor events intel: Update IvyBridge events to V20 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 21/43] perf vendor events intel: Update IvyTown " Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 22/43] perf vendor events intel: Update Silvermont events to V14 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 23/43] perf vendor events intel: Update Skylake events to V36 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 24/43] perf vendor events intel: Update SkylakeX events to V1.06 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 25/43] perf vendor events intel: Update BroadwellDE events to V7 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 26/43] perf vendor events intel: Update IvyBridge files to V20 Arnaldo Carvalho de Melo
2018-01-23 13:12 ` Arnaldo Carvalho de Melo [this message]
2018-01-23 13:12 ` [PATCH 28/43] perf tools: Integrating the CoreSight decoding library Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 29/43] perf tools: Add initial entry point for decoder CoreSight traces Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 30/43] perf tools: Add processing of coresight metadata Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 31/43] perf tools: Add decoder mechanic to support dumping trace data Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 32/43] perf tools: Add support for decoding CoreSight " Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 33/43] perf tools: Add functionality to communicate with the openCSD decoder Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 34/43] pert tools: Add queue management functionality Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 35/43] perf tools: Add full support for CoreSight trace decoding Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 36/43] perf tools: Add mechanic to synthesise CoreSight trace packets Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 37/43] MAINTAINERS: Adding entry for CoreSight trace decoding Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 38/43] perf bpf: Remove misplaced __maybe_unused attribute Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 39/43] perf trace: Add --print-sample Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 40/43] perf trace: Do not print from time delta for interrupted syscall lines Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 41/43] perf trace beauty futex: Beautify FUTEX_BITSET_MATCH_ANY Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 42/43] perf evlist: Remove fcntl.h from evlist.h Arnaldo Carvalho de Melo
2018-01-23 13:12 ` [PATCH 43/43] perf trace beauty flock: Move to separate object file Arnaldo Carvalho de Melo
2018-01-24 11:15 ` [GIT PULL 00/43] perf/core improvements and changes Ingo Molnar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180123131251.28197-28-acme@kernel.org \
--to=acme@kernel.org \
--cc=acme@redhat.com \
--cc=ak@linux.intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mingo@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).