* [GIT PULL 0/8] perf/core improvements and fixes
@ 2017-10-03 12:55 Arnaldo Carvalho de Melo
2017-10-03 16:38 ` Ingo Molnar
0 siblings, 1 reply; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2017-10-03 12:55 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Arnaldo Carvalho de Melo,
Adrian Hunter, Alexei Starovoitov, Andi Kleen, David Ahern,
Heiko Carstens, He Kuang, Hendrik Brueckner, Jiri Olsa, Kan Liang,
Lukasz Odzioba, Martin Schwidefsky, Namhyung Kim, Peter Zijlstra,
Thomas-Mich Richter, Wang Nan, Arnaldo Carvalho de Melo
Hi Ingo,
I pulled tip/perf/urgent to pick up fixes, please consider
pulling, I've been away for a while, so I'll be harvesting outstanding
patches in the next few days, as well as trying and reviewing more
complex patchkits,
- Arnaldo
Test results at the end of this message, as usual.
The following changes since commit c976a7d6db215481261b63a89a408cb265a9812b:
Merge remote-tracking branch 'tip/perf/urgent' into perf/core, to pick up fixes (2017-10-02 13:58:12 -0300)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.15-20171003
for you to fetch changes up to f6a9820d572bd8384d982357cbad214b3a6c04bb:
perf tests attr: Fix group stat tests (2017-10-03 09:41:45 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
- Multithread the synthesizing of PERF_RECORD_ events for pre-existing
threads in 'perf top', speeding up that phase, greatly improving the
user experience in systems such as Intel's Knights Mill (Kan Liang)
- 'perf test' fixes for the perf_event_attr test case (Jiri Olsa, Thomas Richter)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
----------------------------------------------------------------
Jiri Olsa (2):
perf tests attr: Fix task term values
perf tests attr: Fix group stat tests
Kan Liang (4):
perf tools: Lock to protect namespaces and comm list
perf tools: Lock to protect comm_str rb tree
perf top: Implement multithreading for perf_event__synthesize_threads
perf top: Add option to set the number of thread for event synthesize
Thomas Richter (2):
perf test attr: Fix python error on empty result
perf test attr: Fix ignored test case result
tools/perf/Documentation/perf-top.txt | 3 +
tools/perf/builtin-kvm.c | 3 +-
tools/perf/builtin-record.c | 2 +-
tools/perf/builtin-top.c | 13 +-
tools/perf/builtin-trace.c | 2 +-
tools/perf/tests/attr.c | 2 +-
tools/perf/tests/attr.py | 6 +-
tools/perf/tests/attr/base-record | 2 +-
tools/perf/tests/attr/test-record-group | 1 +
tools/perf/tests/attr/test-record-group-sampling | 2 +-
tools/perf/tests/attr/test-record-group1 | 1 +
tools/perf/tests/attr/test-stat-group | 2 +
tools/perf/tests/attr/test-stat-group1 | 2 +
tools/perf/tests/mmap-thread-lookup.c | 2 +-
tools/perf/util/comm.c | 18 ++-
tools/perf/util/event.c | 163 ++++++++++++++++++-----
tools/perf/util/event.h | 3 +-
tools/perf/util/machine.c | 8 +-
tools/perf/util/machine.h | 9 +-
tools/perf/util/thread.c | 53 +++++++-
tools/perf/util/thread.h | 3 +
tools/perf/util/top.h | 1 +
22 files changed, 249 insertions(+), 52 deletions(-)
Test results:
The first ones are container (docker) based builds of tools/perf with and
without libelf support. Where clang is available, it is also used to build
perf with/without libelf.
The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.
Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.
The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.
Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.
# dm
1 alpine:3.4: Ok
2 alpine:3.5: Ok
3 alpine:3.6: Ok
4 alpine:edge: Ok
5 android-ndk:r12b-arm: Ok
6 android-ndk:r15c-arm: Ok
7 centos:5: Ok
8 centos:6: Ok
9 centos:7: Ok
10 debian:7: Ok
11 debian:8: Ok
12 debian:9: Ok
13 debian:experimental: Ok
14 debian:experimental-x-arm64: Ok
15 debian:experimental-x-mips: Ok
16 debian:experimental-x-mips64: Ok
17 debian:experimental-x-mipsel: Ok
18 fedora:20: Ok
19 fedora:21: Ok
20 fedora:22: Ok
21 fedora:23: Ok
22 fedora:24: Ok
23 fedora:24-x-ARC-uClibc: FAIL
builtin-sched.c: In function 'timehist_sched_switch_event':
builtin-sched.c:2580:1: internal compiler error: in change_address_1, at emit-rtl.c:2150
}
^
Please submit a full bug report,
with preprocessed source if appropriate.
See <https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues> for instructions.
24 fedora:25: Ok
25 fedora:26: Ok
26 fedora:rawhide: Ok
27 mageia:5: Ok
28 opensuse:42.1: Ok
29 opensuse:42.2: Ok
30 opensuse:42.3: Ok
31 opensuse:tumbleweed: Ok
32 oraclelinux:6: Ok
33 oraclelinux:7: Ok
34 ubuntu:12.04.5: Ok
35 ubuntu:14.04.4: Ok
36 ubuntu:14.04.4-x-linaro-arm64: Ok
37 ubuntu:15.10: Ok
38 ubuntu:16.04: Ok
39 ubuntu:16.04-x-arm: Ok
40 ubuntu:16.04-x-arm64: Ok
41 ubuntu:16.04-x-powerpc: Ok
42 ubuntu:16.04-x-powerpc64: Ok
43 ubuntu:16.04-x-powerpc64el: Ok
44 ubuntu:16.04-x-s390: Ok
# uname -a
Linux jouet 4.13.0+ #3 SMP Mon Sep 25 11:51:22 -03 2017 x86_64 x86_64 x86_64 GNU/Linux
# perf test
1: vmlinux symtab matches kallsyms : Ok
2: Detect openat syscall event : Ok
3: Detect openat syscall event on all cpus : Ok
4: Read samples using the mmap interface : Ok
5: Test data source output : Ok
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
8: PERF_RECORD_* events & perf_sample fields : Ok
9: Parse perf pmu format : Ok
10: DSO data read : Ok
11: DSO data cache : Ok
12: DSO data reopen : Ok
13: Roundtrip evsel->name : Ok
14: Parse sched tracepoints fields : Ok
15: syscalls:sys_enter_openat event fields : Ok
16: Setup struct perf_event_attr : Ok
17: Match and link multiple hists : Ok
18: 'import perf' in python : Ok
19: Breakpoint overflow signal handler : Ok
20: Breakpoint overflow sampling : Ok
21: Number of exit events of a simple workload : Ok
22: Software clock events period values : Ok
23: Object code reading : Ok
24: Sample parsing : Ok
25: Use a dummy software event to keep tracking : Ok
26: Parse with no sample_id_all bit set : Ok
27: Filter hist entries : Ok
28: Lookup mmap thread : Ok
29: Share thread mg : Ok
30: Sort output of hist entries : Ok
31: Cumulate child hist entries : Ok
32: Track with sched_switch : Ok
33: Filter fds with revents mask in a fdarray : Ok
34: Add fd to a fdarray, making it autogrow : Ok
35: kmod_path__parse : Ok
36: Thread map : Ok
37: LLVM search and compile :
37.1: Basic BPF llvm compile : Ok
37.2: kbuild searching : Ok
37.3: Compile source for BPF prologue generation : Ok
37.4: Compile source for BPF relocation : Ok
38: Session topology : Ok
39: BPF filter :
39.1: Basic BPF filtering : Ok
39.2: BPF pinning : Ok
39.3: BPF prologue generation : Ok
39.4: BPF relocation checker : Ok
40: Synthesize thread map : Ok
41: Remove thread map : Ok
42: Synthesize cpu map : Ok
43: Synthesize stat config : Ok
44: Synthesize stat : Ok
45: Synthesize stat round : Ok
46: Synthesize attr update : Ok
47: Event times : Ok
48: Read backward ring buffer : Ok
49: Print cpu map : Ok
50: Probe SDT events : Ok
51: is_printable_array : Ok
52: Print bitmap : Ok
53: perf hooks : Ok
54: builtin clang support : Skip (not compiled in)
55: unit_number__scnprintf : Ok
56: x86 rdpmc : Ok
57: Convert perf time to TSC : Ok
58: DWARF unwind : Ok
59: x86 instruction decoder - new instructions : Ok
60: Use vfs_getname probe to get syscall args filenames : Ok
61: probe libc's inet_pton & backtrace it with ping : Ok
62: Check open filename arg using perf trace + vfs_getname: Ok
63: Add vfs_getname probe to get syscall args filenames : Ok
#
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [GIT PULL 0/8] perf/core improvements and fixes
2017-10-03 12:55 Arnaldo Carvalho de Melo
@ 2017-10-03 16:38 ` Ingo Molnar
0 siblings, 0 replies; 12+ messages in thread
From: Ingo Molnar @ 2017-10-03 16:38 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: linux-kernel, linux-perf-users, Adrian Hunter, Alexei Starovoitov,
Andi Kleen, David Ahern, Heiko Carstens, He Kuang,
Hendrik Brueckner, Jiri Olsa, Kan Liang, Lukasz Odzioba,
Martin Schwidefsky, Namhyung Kim, Peter Zijlstra,
Thomas-Mich Richter, Wang Nan, Arnaldo Carvalho de Melo
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> Hi Ingo,
>
> I pulled tip/perf/urgent to pick up fixes, please consider
> pulling, I've been away for a while, so I'll be harvesting outstanding
> patches in the next few days, as well as trying and reviewing more
> complex patchkits,
>
> - Arnaldo
>
> Test results at the end of this message, as usual.
>
> The following changes since commit c976a7d6db215481261b63a89a408cb265a9812b:
>
> Merge remote-tracking branch 'tip/perf/urgent' into perf/core, to pick up fixes (2017-10-02 13:58:12 -0300)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.15-20171003
>
> for you to fetch changes up to f6a9820d572bd8384d982357cbad214b3a6c04bb:
>
> perf tests attr: Fix group stat tests (2017-10-03 09:41:45 -0300)
>
> ----------------------------------------------------------------
> perf/core improvements and fixes:
>
> - Multithread the synthesizing of PERF_RECORD_ events for pre-existing
> threads in 'perf top', speeding up that phase, greatly improving the
> user experience in systems such as Intel's Knights Mill (Kan Liang)
>
> - 'perf test' fixes for the perf_event_attr test case (Jiri Olsa, Thomas Richter)
>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> ----------------------------------------------------------------
> Jiri Olsa (2):
> perf tests attr: Fix task term values
> perf tests attr: Fix group stat tests
>
> Kan Liang (4):
> perf tools: Lock to protect namespaces and comm list
> perf tools: Lock to protect comm_str rb tree
> perf top: Implement multithreading for perf_event__synthesize_threads
> perf top: Add option to set the number of thread for event synthesize
>
> Thomas Richter (2):
> perf test attr: Fix python error on empty result
> perf test attr: Fix ignored test case result
>
> tools/perf/Documentation/perf-top.txt | 3 +
> tools/perf/builtin-kvm.c | 3 +-
> tools/perf/builtin-record.c | 2 +-
> tools/perf/builtin-top.c | 13 +-
> tools/perf/builtin-trace.c | 2 +-
> tools/perf/tests/attr.c | 2 +-
> tools/perf/tests/attr.py | 6 +-
> tools/perf/tests/attr/base-record | 2 +-
> tools/perf/tests/attr/test-record-group | 1 +
> tools/perf/tests/attr/test-record-group-sampling | 2 +-
> tools/perf/tests/attr/test-record-group1 | 1 +
> tools/perf/tests/attr/test-stat-group | 2 +
> tools/perf/tests/attr/test-stat-group1 | 2 +
> tools/perf/tests/mmap-thread-lookup.c | 2 +-
> tools/perf/util/comm.c | 18 ++-
> tools/perf/util/event.c | 163 ++++++++++++++++++-----
> tools/perf/util/event.h | 3 +-
> tools/perf/util/machine.c | 8 +-
> tools/perf/util/machine.h | 9 +-
> tools/perf/util/thread.c | 53 +++++++-
> tools/perf/util/thread.h | 3 +
> tools/perf/util/top.h | 1 +
> 22 files changed, 249 insertions(+), 52 deletions(-)
Pulled, thanks a lot Arnaldo!
Ingo
^ permalink raw reply [flat|nested] 12+ messages in thread
* [GIT PULL 0/8] perf/core improvements and fixes
@ 2018-03-28 18:49 Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 1/8] perf build: Fix check-headers.sh opts assignment Arnaldo Carvalho de Melo
` (8 more replies)
0 siblings, 9 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Arnaldo Carvalho de Melo,
Adrian Hunter, Alexander Shishkin, David Ahern, Heiko Carstens,
Hendrik Brueckner, Jiri Olsa, Kan Liang, Martin Schwidefsky,
Namhyung Kim, Peter Zijlstra, Thomas Richter, Wang Nan,
Arnaldo Carvalho de Melo
Hi Ingo,
Please consider pulling,
- Arnaldo
Test results at the end of this message, as usual.
The following changes since commit 631fe154edb0a37308d0116a0f9b7bba9dca6218:
perf/x86: Update rdpmc_always_available static key to the modern API (2018-03-27 07:53:00 +0200)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180328
for you to fetch changes up to 109d59b900e78834c66657dd4748fcedb9a1fe8d:
perf vendor events s390: Add JSON files for IBM z14 (2018-03-27 13:13:39 -0300)
----------------------------------------------------------------
perf/core improvements and fixes:
- Be consistent when checking if a perf_mmap instance had
its ring buffer unmmaped, fixing segfaults noticed in
'perf trace' (Kan Liang, Arnaldo Carvalho de Melo)
- Avoid adding the same option multiple times to the 'diff'
command in check-headers.sh (Jiri Olsa)
- Add vendor event files (JSON format) to various IBM
s390 models (z10EC, z10BC, z196, zEC12, zBC12, z13
and z14) (Thomas Richter)
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
----------------------------------------------------------------
Arnaldo Carvalho de Melo (1):
perf mmap: Be consistent when checking for an unmaped ring buffer
Jiri Olsa (1):
perf build: Fix check-headers.sh opts assignment
Kan Liang (1):
perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()
Thomas Richter (5):
perf vendor events s390: Add JSON files for IBM z10EC z10BC
perf vendor events s390: Add JSON files for IBM z196
perf vendor events s390: Add JSON files for IBM zEC12 zBC12
perf vendor events s390: Add JSON files for IBM z13
perf vendor events s390: Add JSON files for IBM z14
tools/perf/check-headers.sh | 1 +
tools/perf/pmu-events/arch/s390/cf_z10/basic.json | 74 +++++
tools/perf/pmu-events/arch/s390/cf_z10/crypto.json | 98 ++++++
.../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++
tools/perf/pmu-events/arch/s390/cf_z13/basic.json | 74 +++++
tools/perf/pmu-events/arch/s390/cf_z13/crypto.json | 98 ++++++
.../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/cf_z14/basic.json | 50 +++
tools/perf/pmu-events/arch/s390/cf_z14/crypto.json | 98 ++++++
.../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++
tools/perf/pmu-events/arch/s390/cf_z196/basic.json | 74 +++++
.../perf/pmu-events/arch/s390/cf_z196/crypto.json | 98 ++++++
.../pmu-events/arch/s390/cf_z196/extended.json | 146 +++++++++
.../perf/pmu-events/arch/s390/cf_zec12/basic.json | 74 +++++
.../perf/pmu-events/arch/s390/cf_zec12/crypto.json | 98 ++++++
.../pmu-events/arch/s390/cf_zec12/extended.json | 212 +++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 6 +
tools/perf/util/mmap.c | 19 +-
18 files changed, 1987 insertions(+), 1 deletion(-)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv
Test results:
The first ones are container (docker) based builds of tools/perf with and
without libelf support. Where clang is available, it is also used to build
perf with/without libelf.
The objtool and samples/bpf/ builds are disabled now that I'm switching from
using the sources in a local volume to fetching them from a http server to
build it inside the container, to make it easier to build in a container cluster.
Those will come back later.
Several are cross builds, the ones with -x-ARCH and the android one, and those
may not have all the features built, due to lack of multi-arch devel packages,
available and being used so far on just a few, like
debian:experimental-x-{arm64,mipsel}.
The 'perf test' one will perform a variety of tests exercising
tools/perf/util/, tools/lib/{bpf,traceevent,etc}, as well as run perf commands
with a variety of command line event specifications to then intercept the
sys_perf_event syscall to check that the perf_event_attr fields are set up as
expected, among a variety of other unit tests.
Then there is the 'make -C tools/perf build-test' ones, that build tools/perf/
with a variety of feature sets, exercising the build with an incomplete set of
features as well as with a complete one. It is planned to have it run on each
of the containers mentioned above, using some container orchestration
infrastructure. Get in contact if interested in helping having this in place.
# docker images | grep none
# time dm
1 alpine:3.4 : Ok gcc (Alpine 5.3.0) 5.3.0
2 alpine:3.5 : Ok gcc (Alpine 6.2.1) 6.2.1 20160822
3 alpine:3.6 : Ok gcc (Alpine 6.3.0) 6.3.0
4 alpine:3.7 : Ok gcc (Alpine 6.4.0) 6.4.0
5 alpine:edge : Ok gcc (Alpine 6.4.0) 6.4.0
6 amazonlinux:1 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-11)
7 amazonlinux:2 : Ok gcc (GCC) 7.2.1 20170915 (Red Hat 7.2.1-2)
8 android-ndk:r12b-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
9 android-ndk:r15c-arm : Ok arm-linux-androideabi-gcc (GCC) 4.9.x 20150123 (prerelease)
10 centos:5 : Ok gcc (GCC) 4.1.2 20080704 (Red Hat 4.1.2-55)
11 centos:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
12 centos:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16)
13 debian:7 : Ok gcc (Debian 4.7.2-5) 4.7.2
14 debian:8 : Ok gcc (Debian 4.9.2-10+deb8u1) 4.9.2
15 debian:9 : Ok gcc (Debian 6.3.0-18+deb9u1) 6.3.0 20170516
16 debian:experimental : Ok gcc (Debian 7.3.0-12) 7.3.0
17 debian:experimental-x-arm64 : Ok aarch64-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
18 debian:experimental-x-mips : Ok mips-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
19 debian:experimental-x-mips64 : Ok mips64-linux-gnuabi64-gcc (Debian 7.3.0-11) 7.3.0
20 debian:experimental-x-mipsel : Ok mipsel-linux-gnu-gcc (Debian 7.3.0-12) 7.3.0
21 fedora:20 : Ok gcc (GCC) 4.8.3 20140911 (Red Hat 4.8.3-7)
22 fedora:21 : Ok gcc (GCC) 4.9.2 20150212 (Red Hat 4.9.2-6)
23 fedora:22 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
24 fedora:23 : Ok gcc (GCC) 5.3.1 20160406 (Red Hat 5.3.1-6)
25 fedora:24 : Ok gcc (GCC) 6.3.1 20161221 (Red Hat 6.3.1-1)
26 fedora:24-x-ARC-uClibc : Ok arc-linux-gcc (ARCompact ISA Linux uClibc toolchain 2017.09-rc2) 7.1.1 20170710
27 fedora:25 : Ok gcc (GCC) 6.4.1 20170727 (Red Hat 6.4.1-1)
28 fedora:26 : Ok gcc (GCC) 7.3.1 20180130 (Red Hat 7.3.1-2)
29 fedora:27 : Ok gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5)
30 fedora:rawhide : Ok gcc (GCC) 8.0.1 20180222 (Red Hat 8.0.1-0.16)
31 gentoo-stage3-amd64:latest : Ok gcc (Gentoo 6.4.0-r1 p1.3) 6.4.0
32 mageia:5 : Ok gcc (GCC) 4.9.2
33 mageia:6 : Ok gcc (Mageia 5.5.0-1.mga6) 5.5.0
34 opensuse:42.1 : Ok gcc (SUSE Linux) 4.8.5
35 opensuse:42.2 : Ok gcc (SUSE Linux) 4.8.5
36 opensuse:42.3 : Ok gcc (SUSE Linux) 4.8.5
37 opensuse:tumbleweed : Ok gcc (SUSE Linux) 7.3.0
38 oraclelinux:6 : Ok gcc (GCC) 4.4.7 20120313 (Red Hat 4.4.7-18)
39 oraclelinux:7 : Ok gcc (GCC) 4.8.5 20150623 (Red Hat 4.8.5-16.0.3)
40 ubuntu:12.04.5 : Ok gcc (Ubuntu/Linaro 4.6.3-1ubuntu5) 4.6.3
41 ubuntu:14.04.4 : Ok gcc (Ubuntu 4.8.4-2ubuntu1~14.04.3) 4.8.4
42 ubuntu:14.04.4-x-linaro-arm64 : Ok aarch64-linux-gnu-gcc (Linaro GCC 5.4-2017.05) 5.4.1 20170404
43 ubuntu:15.04 : Ok gcc (Ubuntu 4.9.2-10ubuntu13) 4.9.2
44 ubuntu:16.04 : Ok gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
45 ubuntu:16.04-x-arm : Ok arm-linux-gnueabihf-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
46 ubuntu:16.04-x-arm64 : Ok aarch64-linux-gnu-gcc (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
47 ubuntu:16.04-x-powerpc : Ok powerpc-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
48 ubuntu:16.04-x-powerpc64 : Ok powerpc64-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
49 ubuntu:16.04-x-powerpc64el : Ok powerpc64le-linux-gnu-gcc (Ubuntu/IBM 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
50 ubuntu:16.04-x-s390 : Ok s390x-linux-gnu-gcc (Ubuntu 5.4.0-6ubuntu1~16.04.9) 5.4.0 20160609
51 ubuntu:16.10 : Ok gcc (Ubuntu 6.2.0-5ubuntu12) 6.2.0 20161005
52 ubuntu:17.04 : Ok gcc (Ubuntu 6.3.0-12ubuntu2) 6.3.0 20170406
53 ubuntu:17.10 : Ok gcc (Ubuntu 7.2.0-8ubuntu3) 7.2.0
54 ubuntu:18.04 : Ok gcc (Ubuntu 7.2.0-16ubuntu1) 7.2.0
#
# uname -r
4.16.0-rc7
# perf test
1: vmlinux symtab matches kallsyms : Ok
2: Detect openat syscall event : Ok
3: Detect openat syscall event on all cpus : Ok
4: Read samples using the mmap interface : Ok
5: Test data source output : Ok
6: Parse event definition strings : Ok
7: Simple expression parser : Ok
8: PERF_RECORD_* events & perf_sample fields : Ok
9: Parse perf pmu format : Ok
10: DSO data read : Ok
11: DSO data cache : Ok
12: DSO data reopen : Ok
13: Roundtrip evsel->name : Ok
14: Parse sched tracepoints fields : Ok
15: syscalls:sys_enter_openat event fields : Ok
16: Setup struct perf_event_attr : Ok
17: Match and link multiple hists : Ok
18: 'import perf' in python : Ok
19: Breakpoint overflow signal handler : Ok
20: Breakpoint overflow sampling : Ok
21: Breakpoint accounting : Skip
22: Number of exit events of a simple workload : Ok
23: Software clock events period values : Ok
24: Object code reading : Ok
25: Sample parsing : Ok
26: Use a dummy software event to keep tracking : Ok
27: Parse with no sample_id_all bit set : Ok
28: Filter hist entries : Ok
29: Lookup mmap thread : Ok
30: Share thread mg : Ok
31: Sort output of hist entries : Ok
32: Cumulate child hist entries : Ok
33: Track with sched_switch : Ok
34: Filter fds with revents mask in a fdarray : Ok
35: Add fd to a fdarray, making it autogrow : Ok
36: kmod_path__parse : Ok
37: Thread map : Ok
38: LLVM search and compile :
38.1: Basic BPF llvm compile : Ok
38.2: kbuild searching : Ok
38.3: Compile source for BPF prologue generation : Ok
38.4: Compile source for BPF relocation : Ok
39: Session topology : Ok
40: BPF filter :
40.1: Basic BPF filtering : Ok
40.2: BPF pinning : Ok
40.3: BPF prologue generation : Ok
40.4: BPF relocation checker : Ok
41: Synthesize thread map : Ok
42: Remove thread map : Ok
43: Synthesize cpu map : Ok
44: Synthesize stat config : Ok
45: Synthesize stat : Ok
46: Synthesize stat round : Ok
47: Synthesize attr update : Ok
48: Event times : Ok
49: Read backward ring buffer : Ok
50: Print cpu map : Ok
51: Probe SDT events : Ok
52: is_printable_array : Ok
53: Print bitmap : Ok
54: perf hooks : Ok
55: builtin clang support : Skip (not compiled in)
56: unit_number__scnprintf : Ok
57: mem2node : Ok
58: x86 rdpmc : Ok
59: Convert perf time to TSC : Ok
60: DWARF unwind : Ok
61: x86 instruction decoder - new instructions : Ok
62: Use vfs_getname probe to get syscall args filenames : Ok
63: probe libc's inet_pton & backtrace it with ping : Ok
64: Check open filename arg using perf trace + vfs_getname: Ok
65: probe libc's inet_pton & backtrace it with ping : Ok
66: Add vfs_getname probe to get syscall args filenames : Ok
#
$ make -C tools/perf build-test
make: Entering directory '/home/acme/git/perf/tools/perf'
- tarpkg: ./tests/perf-targz-src-pkg .
make_no_ui_O: make NO_NEWT=1 NO_SLANG=1 NO_GTK2=1
make_no_libperl_O: make NO_LIBPERL=1
make_no_libbionic_O: make NO_LIBBIONIC=1
make_install_prefix_O: make install prefix=/tmp/krava
make_perf_o_O: make perf.o
make_no_libpython_O: make NO_LIBPYTHON=1
make_tags_O: make tags
make_install_O: make install
make_doc_O: make doc
make_util_pmu_bison_o_O: make util/pmu-bison.o
make_no_libelf_O: make NO_LIBELF=1
make_install_bin_O: make install-bin
make_no_backtrace_O: make NO_BACKTRACE=1
make_no_gtk2_O: make NO_GTK2=1
make_no_slang_O: make NO_SLANG=1
make_no_libdw_dwarf_unwind_O: make NO_LIBDW_DWARF_UNWIND=1
make_with_babeltrace_O: make LIBBABELTRACE=1
make_help_O: make help
make_no_demangle_O: make NO_DEMANGLE=1
make_no_libbpf_O: make NO_LIBBPF=1
make_minimal_O: make NO_LIBPERL=1 NO_LIBPYTHON=1 NO_NEWT=1 NO_GTK2=1 NO_DEMANGLE=1 NO_LIBELF=1 NO_LIBUNWIND=1 NO_BACKTRACE=1 NO_LIBNUMA=1 NO_LIBAUDIT=1 NO_LIBBIONIC=1 NO_LIBDW_DWARF_UNWIND=1 NO_AUXTRACE=1 NO_LIBBPF=1 NO_LIBCRYPTO=1 NO_SDT=1 NO_JVMTI=1
make_clean_all_O: make clean all
make_no_newt_O: make NO_NEWT=1
make_no_libaudit_O: make NO_LIBAUDIT=1
make_no_libunwind_O: make NO_LIBUNWIND=1
make_no_auxtrace_O: make NO_AUXTRACE=1
make_debug_O: make DEBUG=1
make_pure_O: make
make_no_libnuma_O: make NO_LIBNUMA=1
make_no_scripts_O: make NO_LIBPYTHON=1 NO_LIBPERL=1
make_static_O: make LDFLAGS=-static
make_with_clangllvm_O: make LIBCLANGLLVM=1
make_install_prefix_slash_O: make install prefix=/tmp/krava/
make_util_map_o_O: make util/map.o
OK
make: Leaving directory '/home/acme/git/perf/tools/perf'
$
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 1/8] perf build: Fix check-headers.sh opts assignment
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 2/8] perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done() Arnaldo Carvalho de Melo
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Jiri Olsa, Alexander Shishkin,
David Ahern, Namhyung Kim, Peter Zijlstra,
Arnaldo Carvalho de Melo
From: Jiri Olsa <jolsa@kernel.org>
Currently the "opts" variable is not zero-ed and we keep on adding to
it, ending up with:
$ check-headers.sh 2>&1
+ opts=' "-B"'
+ opts=' "-B" "-B"'
+ opts=' "-B" "-B" "-B"'
+ opts=' "-B" "-B" "-B" "-B"'
+ opts=' "-B" "-B" "-B" "-B" "-B"'
+ opts=' "-B" "-B" "-B" "-B" "-B" "-B"'
Fix this by initializing it in the check() function, right before
starting the loop.
Signed-off-by: Jiri Olsa <jolsa@kernel.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20180321140515.2252-1-jolsa@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
| 1 +
1 file changed, 1 insertion(+)
--git a/tools/perf/check-headers.sh b/tools/perf/check-headers.sh
index bf206ffe5c45..9aff89bc7535 100755
--- a/tools/perf/check-headers.sh
+++ b/tools/perf/check-headers.sh
@@ -59,6 +59,7 @@ check () {
file=$1
shift
+ opts=
while [ -n "$*" ]; do
opts="$opts \"$1\""
shift
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 2/8] perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 1/8] perf build: Fix check-headers.sh opts assignment Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 3/8] perf mmap: Be consistent when checking for an unmaped ring buffer Arnaldo Carvalho de Melo
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Kan Liang, Jiri Olsa,
Namhyung Kim, Wang Nan, Arnaldo Carvalho de Melo
From: Kan Liang <kan.liang@linux.intel.com>
There is a segmentation fault when running 'perf trace'. For example:
[root@jouet e]# perf trace -e *chdir -o /tmp/bla perf report --ignore-vmlinux -i ../perf.data
The perf_mmap__consume() could unmap the mmap. It needs to check the
refcnt in perf_mmap__read_done().
Reported-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Wang Nan <wangnan0@huawei.com>
Fixes: ee023de05f35 ("perf mmap: Introduce perf_mmap__read_done()")
Link: http://lkml.kernel.org/r/1522071729-16776-1-git-send-email-kan.liang@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/util/mmap.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
index 38ca3ffb9d61..f6cfc52ff1fe 100644
--- a/tools/perf/util/mmap.c
+++ b/tools/perf/util/mmap.c
@@ -317,5 +317,11 @@ int perf_mmap__push(struct perf_mmap *md, void *to,
*/
void perf_mmap__read_done(struct perf_mmap *map)
{
+ /*
+ * Check if event was unmapped due to a POLLHUP/POLLERR.
+ */
+ if (!refcount_read(&map->refcnt))
+ return;
+
map->prev = perf_mmap__read_head(map);
}
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 3/8] perf mmap: Be consistent when checking for an unmaped ring buffer
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 1/8] perf build: Fix check-headers.sh opts assignment Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 2/8] perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done() Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 4/8] perf vendor events s390: Add JSON files for IBM z10EC z10BC Arnaldo Carvalho de Melo
` (5 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Arnaldo Carvalho de Melo,
Adrian Hunter, David Ahern, Jiri Olsa, Kan Liang, Namhyung Kim,
Wang Nan
From: Arnaldo Carvalho de Melo <acme@redhat.com>
The previous patch is insufficient to cure the reported 'perf trace'
segfault, as it only cures the perf_mmap__read_done() case, moving the
segfault to perf_mmap__read_init() functio, fix it by doing the same
refcount check.
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Wang Nan <wangnan0@huawei.com>
Fixes: 8872481bd048 ("perf mmap: Introduce perf_mmap__read_init()")
Link: https://lkml.kernel.org/r/20180326144127.GF18897@kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/util/mmap.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/tools/perf/util/mmap.c b/tools/perf/util/mmap.c
index f6cfc52ff1fe..fc832676a798 100644
--- a/tools/perf/util/mmap.c
+++ b/tools/perf/util/mmap.c
@@ -234,7 +234,7 @@ static int overwrite_rb_find_range(void *buf, int mask, u64 *start, u64 *end)
/*
* Report the start and end of the available data in ringbuffer
*/
-int perf_mmap__read_init(struct perf_mmap *md)
+static int __perf_mmap__read_init(struct perf_mmap *md)
{
u64 head = perf_mmap__read_head(md);
u64 old = md->prev;
@@ -268,6 +268,17 @@ int perf_mmap__read_init(struct perf_mmap *md)
return 0;
}
+int perf_mmap__read_init(struct perf_mmap *map)
+{
+ /*
+ * Check if event was unmapped due to a POLLHUP/POLLERR.
+ */
+ if (!refcount_read(&map->refcnt))
+ return -ENOENT;
+
+ return __perf_mmap__read_init(map);
+}
+
int perf_mmap__push(struct perf_mmap *md, void *to,
int push(void *to, void *buf, size_t size))
{
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 4/8] perf vendor events s390: Add JSON files for IBM z10EC z10BC
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (2 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 3/8] perf mmap: Be consistent when checking for an unmaped ring buffer Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 5/8] perf vendor events s390: Add JSON files for IBM z196 Arnaldo Carvalho de Melo
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Thomas Richter, Heiko Carstens,
Martin Schwidefsky, Arnaldo Carvalho de Melo
From: Thomas Richter <tmricht@linux.vnet.ibm.com>
Add CPU measurement counter facility event description files (JSON
files) for IBM z10EC and z10BC.
Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-1-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/s390/cf_z10/basic.json | 74 ++++++++++++++
tools/perf/pmu-events/arch/s390/cf_z10/crypto.json | 98 ++++++++++++++++++
.../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 2 +
4 files changed, 284 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/basic.json b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/basic.json
@@ -0,0 +1,74 @@
+[
+ {
+ "EventCode": "0",
+ "EventName": "CPU_CYCLES",
+ "BriefDescription": "CPU Cycles",
+ "PublicDescription": "Cycle Count"
+ },
+ {
+ "EventCode": "1",
+ "EventName": "INSTRUCTIONS",
+ "BriefDescription": "Instructions",
+ "PublicDescription": "Instruction Count"
+ },
+ {
+ "EventCode": "2",
+ "EventName": "L1I_DIR_WRITES",
+ "BriefDescription": "L1I Directory Writes",
+ "PublicDescription": "Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "3",
+ "EventName": "L1I_PENALTY_CYCLES",
+ "BriefDescription": "L1I Penalty Cycles",
+ "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "4",
+ "EventName": "L1D_DIR_WRITES",
+ "BriefDescription": "L1D Directory Writes",
+ "PublicDescription": "Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "5",
+ "EventName": "L1D_PENALTY_CYCLES",
+ "BriefDescription": "L1D Penalty Cycles",
+ "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "32",
+ "EventName": "PROBLEM_STATE_CPU_CYCLES",
+ "BriefDescription": "Problem-State CPU Cycles",
+ "PublicDescription": "Problem-State Cycle Count"
+ },
+ {
+ "EventCode": "33",
+ "EventName": "PROBLEM_STATE_INSTRUCTIONS",
+ "BriefDescription": "Problem-State Instructions",
+ "PublicDescription": "Problem-State Instruction Count"
+ },
+ {
+ "EventCode": "34",
+ "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+ "BriefDescription": "Problem-State L1I Directory Writes",
+ "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "35",
+ "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1I Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "36",
+ "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+ "BriefDescription": "Problem-State L1D Directory Writes",
+ "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "37",
+ "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1D Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
@@ -0,0 +1,98 @@
+[
+ {
+ "EventCode": "64",
+ "EventName": "PRNG_FUNCTIONS",
+ "BriefDescription": "PRNG Functions",
+ "PublicDescription": "Total number of the PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "65",
+ "EventName": "PRNG_CYCLES",
+ "BriefDescription": "PRNG Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "66",
+ "EventName": "PRNG_BLOCKED_FUNCTIONS",
+ "BriefDescription": "PRNG Blocked Functions",
+ "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "67",
+ "EventName": "PRNG_BLOCKED_CYCLES",
+ "BriefDescription": "PRNG Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "68",
+ "EventName": "SHA_FUNCTIONS",
+ "BriefDescription": "SHA Functions",
+ "PublicDescription": "Total number of SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "69",
+ "EventName": "SHA_CYCLES",
+ "BriefDescription": "SHA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "70",
+ "EventName": "SHA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "SHA Blocked Functions",
+ "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "71",
+ "EventName": "SHA_BLOCKED_CYCLES",
+ "BriefDescription": "SHA Bloced Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "72",
+ "EventName": "DEA_FUNCTIONS",
+ "BriefDescription": "DEA Functions",
+ "PublicDescription": "Total number of the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "73",
+ "EventName": "DEA_CYCLES",
+ "BriefDescription": "DEA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "74",
+ "EventName": "DEA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "DEA Blocked Functions",
+ "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "75",
+ "EventName": "DEA_BLOCKED_CYCLES",
+ "BriefDescription": "DEA Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "76",
+ "EventName": "AES_FUNCTIONS",
+ "BriefDescription": "AES Functions",
+ "PublicDescription": "Total number of AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "77",
+ "EventName": "AES_CYCLES",
+ "BriefDescription": "AES Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "78",
+ "EventName": "AES_BLOCKED_FUNCTIONS",
+ "BriefDescription": "AES Blocked Functions",
+ "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "79",
+ "EventName": "AES_BLOCKED_CYCLES",
+ "BriefDescription": "AES Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z10/extended.json b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
new file mode 100644
index 000000000000..0feedb40f30f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z10/extended.json
@@ -0,0 +1,110 @@
+[
+ {
+ "EventCode": "128",
+ "EventName": "L1I_L2_SOURCED_WRITES",
+ "BriefDescription": "L1I L2 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
+ },
+ {
+ "EventCode": "129",
+ "EventName": "L1D_L2_SOURCED_WRITES",
+ "BriefDescription": "L1D L2 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
+ },
+ {
+ "EventCode": "130",
+ "EventName": "L1I_L3_LOCAL_WRITES",
+ "BriefDescription": "L1I L3 Local Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
+ },
+ {
+ "EventCode": "131",
+ "EventName": "L1D_L3_LOCAL_WRITES",
+ "BriefDescription": "L1D L3 Local Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
+ },
+ {
+ "EventCode": "132",
+ "EventName": "L1I_L3_REMOTE_WRITES",
+ "BriefDescription": "L1I L3 Remote Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
+ },
+ {
+ "EventCode": "133",
+ "EventName": "L1D_L3_REMOTE_WRITES",
+ "BriefDescription": "L1D L3 Remote Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
+ },
+ {
+ "EventCode": "134",
+ "EventName": "L1D_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1D Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+ },
+ {
+ "EventCode": "135",
+ "EventName": "L1I_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1I Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
+ },
+ {
+ "EventCode": "136",
+ "EventName": "L1D_RO_EXCL_WRITES",
+ "BriefDescription": "L1D Read-only Exclusive Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+ },
+ {
+ "EventCode": "137",
+ "EventName": "L1I_CACHELINE_INVALIDATES",
+ "BriefDescription": "L1I Cacheline Invalidates",
+ "PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
+ },
+ {
+ "EventCode": "138",
+ "EventName": "ITLB1_WRITES",
+ "BriefDescription": "ITLB1 Writes",
+ "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "139",
+ "EventName": "DTLB1_WRITES",
+ "BriefDescription": "DTLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "140",
+ "EventName": "TLB2_PTE_WRITES",
+ "BriefDescription": "TLB2 PTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+ },
+ {
+ "EventCode": "141",
+ "EventName": "TLB2_CRSTE_WRITES",
+ "BriefDescription": "TLB2 CRSTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+ },
+ {
+ "EventCode": "142",
+ "EventName": "TLB2_CRSTE_HPAGE_WRITES",
+ "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+ },
+ {
+ "EventCode": "145",
+ "EventName": "ITLB1_MISSES",
+ "BriefDescription": "ITLB1 Misses",
+ "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
+ },
+ {
+ "EventCode": "146",
+ "EventName": "DTLB1_MISSES",
+ "BriefDescription": "DTLB1 Misses",
+ "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
+ },
+ {
+ "EventCode": "147",
+ "EventName": "L2C_STORES_SENT",
+ "BriefDescription": "L2C Stores Sent",
+ "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
new file mode 100644
index 000000000000..735159593c2c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -0,0 +1,2 @@
+Family-model,Version,Filename,EventType
+209[78],1,cf_z10,core
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 5/8] perf vendor events s390: Add JSON files for IBM z196
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (3 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 4/8] perf vendor events s390: Add JSON files for IBM z10EC z10BC Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 6/8] perf vendor events s390: Add JSON files for IBM zEC12 zBC12 Arnaldo Carvalho de Melo
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Thomas Richter, Heiko Carstens,
Martin Schwidefsky, Arnaldo Carvalho de Melo
From: Thomas Richter <tmricht@linux.vnet.ibm.com>
Add CPU measurement counter facility event description files (json
files) for IBM z196.
Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-2-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/s390/cf_z196/basic.json | 74 +++++++++++
.../perf/pmu-events/arch/s390/cf_z196/crypto.json | 98 ++++++++++++++
.../pmu-events/arch/s390/cf_z196/extended.json | 146 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 1 +
4 files changed, 319 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/basic.json b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/basic.json
@@ -0,0 +1,74 @@
+[
+ {
+ "EventCode": "0",
+ "EventName": "CPU_CYCLES",
+ "BriefDescription": "CPU Cycles",
+ "PublicDescription": "Cycle Count"
+ },
+ {
+ "EventCode": "1",
+ "EventName": "INSTRUCTIONS",
+ "BriefDescription": "Instructions",
+ "PublicDescription": "Instruction Count"
+ },
+ {
+ "EventCode": "2",
+ "EventName": "L1I_DIR_WRITES",
+ "BriefDescription": "L1I Directory Writes",
+ "PublicDescription": "Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "3",
+ "EventName": "L1I_PENALTY_CYCLES",
+ "BriefDescription": "L1I Penalty Cycles",
+ "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "4",
+ "EventName": "L1D_DIR_WRITES",
+ "BriefDescription": "L1D Directory Writes",
+ "PublicDescription": "Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "5",
+ "EventName": "L1D_PENALTY_CYCLES",
+ "BriefDescription": "L1D Penalty Cycles",
+ "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "32",
+ "EventName": "PROBLEM_STATE_CPU_CYCLES",
+ "BriefDescription": "Problem-State CPU Cycles",
+ "PublicDescription": "Problem-State Cycle Count"
+ },
+ {
+ "EventCode": "33",
+ "EventName": "PROBLEM_STATE_INSTRUCTIONS",
+ "BriefDescription": "Problem-State Instructions",
+ "PublicDescription": "Problem-State Instruction Count"
+ },
+ {
+ "EventCode": "34",
+ "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+ "BriefDescription": "Problem-State L1I Directory Writes",
+ "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "35",
+ "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1I Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "36",
+ "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+ "BriefDescription": "Problem-State L1D Directory Writes",
+ "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "37",
+ "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1D Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
@@ -0,0 +1,98 @@
+[
+ {
+ "EventCode": "64",
+ "EventName": "PRNG_FUNCTIONS",
+ "BriefDescription": "PRNG Functions",
+ "PublicDescription": "Total number of the PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "65",
+ "EventName": "PRNG_CYCLES",
+ "BriefDescription": "PRNG Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "66",
+ "EventName": "PRNG_BLOCKED_FUNCTIONS",
+ "BriefDescription": "PRNG Blocked Functions",
+ "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "67",
+ "EventName": "PRNG_BLOCKED_CYCLES",
+ "BriefDescription": "PRNG Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "68",
+ "EventName": "SHA_FUNCTIONS",
+ "BriefDescription": "SHA Functions",
+ "PublicDescription": "Total number of SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "69",
+ "EventName": "SHA_CYCLES",
+ "BriefDescription": "SHA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "70",
+ "EventName": "SHA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "SHA Blocked Functions",
+ "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "71",
+ "EventName": "SHA_BLOCKED_CYCLES",
+ "BriefDescription": "SHA Bloced Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "72",
+ "EventName": "DEA_FUNCTIONS",
+ "BriefDescription": "DEA Functions",
+ "PublicDescription": "Total number of the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "73",
+ "EventName": "DEA_CYCLES",
+ "BriefDescription": "DEA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "74",
+ "EventName": "DEA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "DEA Blocked Functions",
+ "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "75",
+ "EventName": "DEA_BLOCKED_CYCLES",
+ "BriefDescription": "DEA Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "76",
+ "EventName": "AES_FUNCTIONS",
+ "BriefDescription": "AES Functions",
+ "PublicDescription": "Total number of AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "77",
+ "EventName": "AES_CYCLES",
+ "BriefDescription": "AES Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "78",
+ "EventName": "AES_BLOCKED_FUNCTIONS",
+ "BriefDescription": "AES Blocked Functions",
+ "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "79",
+ "EventName": "AES_BLOCKED_CYCLES",
+ "BriefDescription": "AES Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z196/extended.json b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
new file mode 100644
index 000000000000..b6d7fec7c2e7
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z196/extended.json
@@ -0,0 +1,146 @@
+[
+ {
+ "EventCode": "128",
+ "EventName": "L1D_L2_SOURCED_WRITES",
+ "BriefDescription": "L1D L2 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from the Level-2 cache"
+ },
+ {
+ "EventCode": "129",
+ "EventName": "L1I_L2_SOURCED_WRITES",
+ "BriefDescription": "L1I L2 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 cache"
+ },
+ {
+ "EventCode": "130",
+ "EventName": "DTLB1_MISSES",
+ "BriefDescription": "DTLB1 Misses",
+ "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+ },
+ {
+ "EventCode": "131",
+ "EventName": "ITLB1_MISSES",
+ "BriefDescription": "ITLB1 Misses",
+ "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
+ },
+ {
+ "EventCode": "133",
+ "EventName": "L2C_STORES_SENT",
+ "BriefDescription": "L2C Stores Sent",
+ "PublicDescription": "Incremented by one for every store sent to Level-2 cache"
+ },
+ {
+ "EventCode": "134",
+ "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Book L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
+ },
+ {
+ "EventCode": "135",
+ "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+ },
+ {
+ "EventCode": "136",
+ "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+ },
+ {
+ "EventCode": "137",
+ "EventName": "L1D_RO_EXCL_WRITES",
+ "BriefDescription": "L1D Read-only Exclusive Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+ },
+ {
+ "EventCode": "138",
+ "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+ },
+ {
+ "EventCode": "139",
+ "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+ },
+ {
+ "EventCode": "140",
+ "EventName": "DTLB1_HPAGE_WRITES",
+ "BriefDescription": "DTLB1 One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+ },
+ {
+ "EventCode": "141",
+ "EventName": "L1D_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1D Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+ },
+ {
+ "EventCode": "142",
+ "EventName": "L1I_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1I Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
+ },
+ {
+ "EventCode": "143",
+ "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Book L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Book Level-3 cache"
+ },
+ {
+ "EventCode": "144",
+ "EventName": "DTLB1_WRITES",
+ "BriefDescription": "DTLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "145",
+ "EventName": "ITLB1_WRITES",
+ "BriefDescription": "ITLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "146",
+ "EventName": "TLB2_PTE_WRITES",
+ "BriefDescription": "TLB2 PTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+ },
+ {
+ "EventCode": "147",
+ "EventName": "TLB2_CRSTE_HPAGE_WRITES",
+ "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+ },
+ {
+ "EventCode": "148",
+ "EventName": "TLB2_CRSTE_WRITES",
+ "BriefDescription": "TLB2 CRSTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+ },
+ {
+ "EventCode": "150",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
+ },
+ {
+ "EventCode": "152",
+ "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
+ },
+ {
+ "EventCode": "153",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an On Chip Level-3 cache"
+ },
+ {
+ "EventCode": "155",
+ "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index 735159593c2c..b9c673087011 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -1,2 +1,3 @@
Family-model,Version,Filename,EventType
209[78],1,cf_z10,core
+281[78],1,cf_z196,core
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 6/8] perf vendor events s390: Add JSON files for IBM zEC12 zBC12
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (4 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 5/8] perf vendor events s390: Add JSON files for IBM z196 Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 7/8] perf vendor events s390: Add JSON files for IBM z13 Arnaldo Carvalho de Melo
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Thomas Richter, Heiko Carstens,
Martin Schwidefsky, Arnaldo Carvalho de Melo
From: Thomas Richter <tmricht@linux.vnet.ibm.com>
Add CPU measurement counter facility event description files (json
files) for IBM zEC12 and zBC12.
Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-3-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../perf/pmu-events/arch/s390/cf_zec12/basic.json | 74 +++++++
.../perf/pmu-events/arch/s390/cf_zec12/crypto.json | 98 ++++++++++
.../pmu-events/arch/s390/cf_zec12/extended.json | 212 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 1 +
4 files changed, 385 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
@@ -0,0 +1,74 @@
+[
+ {
+ "EventCode": "0",
+ "EventName": "CPU_CYCLES",
+ "BriefDescription": "CPU Cycles",
+ "PublicDescription": "Cycle Count"
+ },
+ {
+ "EventCode": "1",
+ "EventName": "INSTRUCTIONS",
+ "BriefDescription": "Instructions",
+ "PublicDescription": "Instruction Count"
+ },
+ {
+ "EventCode": "2",
+ "EventName": "L1I_DIR_WRITES",
+ "BriefDescription": "L1I Directory Writes",
+ "PublicDescription": "Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "3",
+ "EventName": "L1I_PENALTY_CYCLES",
+ "BriefDescription": "L1I Penalty Cycles",
+ "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "4",
+ "EventName": "L1D_DIR_WRITES",
+ "BriefDescription": "L1D Directory Writes",
+ "PublicDescription": "Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "5",
+ "EventName": "L1D_PENALTY_CYCLES",
+ "BriefDescription": "L1D Penalty Cycles",
+ "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "32",
+ "EventName": "PROBLEM_STATE_CPU_CYCLES",
+ "BriefDescription": "Problem-State CPU Cycles",
+ "PublicDescription": "Problem-State Cycle Count"
+ },
+ {
+ "EventCode": "33",
+ "EventName": "PROBLEM_STATE_INSTRUCTIONS",
+ "BriefDescription": "Problem-State Instructions",
+ "PublicDescription": "Problem-State Instruction Count"
+ },
+ {
+ "EventCode": "34",
+ "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+ "BriefDescription": "Problem-State L1I Directory Writes",
+ "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "35",
+ "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1I Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "36",
+ "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+ "BriefDescription": "Problem-State L1D Directory Writes",
+ "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "37",
+ "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1D Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
@@ -0,0 +1,98 @@
+[
+ {
+ "EventCode": "64",
+ "EventName": "PRNG_FUNCTIONS",
+ "BriefDescription": "PRNG Functions",
+ "PublicDescription": "Total number of the PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "65",
+ "EventName": "PRNG_CYCLES",
+ "BriefDescription": "PRNG Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "66",
+ "EventName": "PRNG_BLOCKED_FUNCTIONS",
+ "BriefDescription": "PRNG Blocked Functions",
+ "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "67",
+ "EventName": "PRNG_BLOCKED_CYCLES",
+ "BriefDescription": "PRNG Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "68",
+ "EventName": "SHA_FUNCTIONS",
+ "BriefDescription": "SHA Functions",
+ "PublicDescription": "Total number of SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "69",
+ "EventName": "SHA_CYCLES",
+ "BriefDescription": "SHA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "70",
+ "EventName": "SHA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "SHA Blocked Functions",
+ "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "71",
+ "EventName": "SHA_BLOCKED_CYCLES",
+ "BriefDescription": "SHA Bloced Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "72",
+ "EventName": "DEA_FUNCTIONS",
+ "BriefDescription": "DEA Functions",
+ "PublicDescription": "Total number of the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "73",
+ "EventName": "DEA_CYCLES",
+ "BriefDescription": "DEA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "74",
+ "EventName": "DEA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "DEA Blocked Functions",
+ "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "75",
+ "EventName": "DEA_BLOCKED_CYCLES",
+ "BriefDescription": "DEA Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "76",
+ "EventName": "AES_FUNCTIONS",
+ "BriefDescription": "AES Functions",
+ "PublicDescription": "Total number of AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "77",
+ "EventName": "AES_CYCLES",
+ "BriefDescription": "AES Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "78",
+ "EventName": "AES_BLOCKED_FUNCTIONS",
+ "BriefDescription": "AES Blocked Functions",
+ "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "79",
+ "EventName": "AES_BLOCKED_CYCLES",
+ "BriefDescription": "AES Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
new file mode 100644
index 000000000000..8682126aabb2
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
@@ -0,0 +1,212 @@
+[
+ {
+ "EventCode": "128",
+ "EventName": "DTLB1_MISSES",
+ "BriefDescription": "DTLB1 Misses",
+ "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+ },
+ {
+ "EventCode": "129",
+ "EventName": "ITLB1_MISSES",
+ "BriefDescription": "ITLB1 Misses",
+ "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
+ },
+ {
+ "EventCode": "130",
+ "EventName": "L1D_L2I_SOURCED_WRITES",
+ "BriefDescription": "L1D L2I Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+ },
+ {
+ "EventCode": "131",
+ "EventName": "L1I_L2I_SOURCED_WRITES",
+ "BriefDescription": "L1I L2I Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+ },
+ {
+ "EventCode": "132",
+ "EventName": "L1D_L2D_SOURCED_WRITES",
+ "BriefDescription": "L1D L2D Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+ },
+ {
+ "EventCode": "133",
+ "EventName": "DTLB1_WRITES",
+ "BriefDescription": "DTLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "135",
+ "EventName": "L1D_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1D Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
+ },
+ {
+ "EventCode": "137",
+ "EventName": "L1I_LMEM_SOURCED_WRITES",
+ "BriefDescription": "L1I Local Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)"
+ },
+ {
+ "EventCode": "138",
+ "EventName": "L1D_RO_EXCL_WRITES",
+ "BriefDescription": "L1D Read-only Exclusive Writes",
+ "PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+ },
+ {
+ "EventCode": "139",
+ "EventName": "DTLB1_HPAGE_WRITES",
+ "BriefDescription": "DTLB1 One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+ },
+ {
+ "EventCode": "140",
+ "EventName": "ITLB1_WRITES",
+ "BriefDescription": "ITLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "141",
+ "EventName": "TLB2_PTE_WRITES",
+ "BriefDescription": "TLB2 PTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+ },
+ {
+ "EventCode": "142",
+ "EventName": "TLB2_CRSTE_HPAGE_WRITES",
+ "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
+ },
+ {
+ "EventCode": "143",
+ "EventName": "TLB2_CRSTE_WRITES",
+ "BriefDescription": "TLB2 CRSTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
+ },
+ {
+ "EventCode": "144",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "145",
+ "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "146",
+ "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Book L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "147",
+ "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+ },
+ {
+ "EventCode": "148",
+ "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+ },
+ {
+ "EventCode": "149",
+ "EventName": "TX_NC_TEND",
+ "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode"
+ },
+ {
+ "EventCode": "150",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "151",
+ "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "152",
+ "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "153",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "154",
+ "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "155",
+ "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Book L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "156",
+ "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache"
+ },
+ {
+ "EventCode": "157",
+ "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Book L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache"
+ },
+ {
+ "EventCode": "158",
+ "EventName": "TX_C_TEND",
+ "BriefDescription": "Completed TEND instructions in constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "159",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "160",
+ "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "161",
+ "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "177",
+ "EventName": "TX_NC_TABORT",
+ "BriefDescription": "Aborted transactions in non-constrained TX mode",
+ "PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode"
+ },
+ {
+ "EventCode": "178",
+ "EventName": "TX_C_TABORT_NO_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+ },
+ {
+ "EventCode": "179",
+ "EventName": "TX_C_TABORT_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index b9c673087011..c57f8e75fa23 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -1,3 +1,4 @@
Family-model,Version,Filename,EventType
209[78],1,cf_z10,core
281[78],1,cf_z196,core
+282[78],1,cf_zec12,core
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 7/8] perf vendor events s390: Add JSON files for IBM z13
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (5 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 6/8] perf vendor events s390: Add JSON files for IBM zEC12 zBC12 Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 8/8] perf vendor events s390: Add JSON files for IBM z14 Arnaldo Carvalho de Melo
2018-03-29 7:23 ` [GIT PULL 0/8] perf/core improvements and fixes Ingo Molnar
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Thomas Richter, Heiko Carstens,
Martin Schwidefsky, Arnaldo Carvalho de Melo
From: Thomas Richter <tmricht@linux.vnet.ibm.com>
Add CPU measurement counter facility event description files (json
files) for IBM z13.
Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-4-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/s390/cf_z13/basic.json | 74 +++++
tools/perf/pmu-events/arch/s390/cf_z13/crypto.json | 98 ++++++
.../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 1 +
4 files changed, 511 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/basic.json b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
new file mode 100644
index 000000000000..8bf16759ca53
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/basic.json
@@ -0,0 +1,74 @@
+[
+ {
+ "EventCode": "0",
+ "EventName": "CPU_CYCLES",
+ "BriefDescription": "CPU Cycles",
+ "PublicDescription": "Cycle Count"
+ },
+ {
+ "EventCode": "1",
+ "EventName": "INSTRUCTIONS",
+ "BriefDescription": "Instructions",
+ "PublicDescription": "Instruction Count"
+ },
+ {
+ "EventCode": "2",
+ "EventName": "L1I_DIR_WRITES",
+ "BriefDescription": "L1I Directory Writes",
+ "PublicDescription": "Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "3",
+ "EventName": "L1I_PENALTY_CYCLES",
+ "BriefDescription": "L1I Penalty Cycles",
+ "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "4",
+ "EventName": "L1D_DIR_WRITES",
+ "BriefDescription": "L1D Directory Writes",
+ "PublicDescription": "Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "5",
+ "EventName": "L1D_PENALTY_CYCLES",
+ "BriefDescription": "L1D Penalty Cycles",
+ "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "32",
+ "EventName": "PROBLEM_STATE_CPU_CYCLES",
+ "BriefDescription": "Problem-State CPU Cycles",
+ "PublicDescription": "Problem-State Cycle Count"
+ },
+ {
+ "EventCode": "33",
+ "EventName": "PROBLEM_STATE_INSTRUCTIONS",
+ "BriefDescription": "Problem-State Instructions",
+ "PublicDescription": "Problem-State Instruction Count"
+ },
+ {
+ "EventCode": "34",
+ "EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
+ "BriefDescription": "Problem-State L1I Directory Writes",
+ "PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "35",
+ "EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1I Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "36",
+ "EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
+ "BriefDescription": "Problem-State L1D Directory Writes",
+ "PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "37",
+ "EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
+ "BriefDescription": "Problem-State L1D Penalty Cycles",
+ "PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
@@ -0,0 +1,98 @@
+[
+ {
+ "EventCode": "64",
+ "EventName": "PRNG_FUNCTIONS",
+ "BriefDescription": "PRNG Functions",
+ "PublicDescription": "Total number of the PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "65",
+ "EventName": "PRNG_CYCLES",
+ "BriefDescription": "PRNG Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "66",
+ "EventName": "PRNG_BLOCKED_FUNCTIONS",
+ "BriefDescription": "PRNG Blocked Functions",
+ "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "67",
+ "EventName": "PRNG_BLOCKED_CYCLES",
+ "BriefDescription": "PRNG Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "68",
+ "EventName": "SHA_FUNCTIONS",
+ "BriefDescription": "SHA Functions",
+ "PublicDescription": "Total number of SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "69",
+ "EventName": "SHA_CYCLES",
+ "BriefDescription": "SHA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "70",
+ "EventName": "SHA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "SHA Blocked Functions",
+ "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "71",
+ "EventName": "SHA_BLOCKED_CYCLES",
+ "BriefDescription": "SHA Bloced Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "72",
+ "EventName": "DEA_FUNCTIONS",
+ "BriefDescription": "DEA Functions",
+ "PublicDescription": "Total number of the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "73",
+ "EventName": "DEA_CYCLES",
+ "BriefDescription": "DEA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "74",
+ "EventName": "DEA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "DEA Blocked Functions",
+ "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "75",
+ "EventName": "DEA_BLOCKED_CYCLES",
+ "BriefDescription": "DEA Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "76",
+ "EventName": "AES_FUNCTIONS",
+ "BriefDescription": "AES Functions",
+ "PublicDescription": "Total number of AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "77",
+ "EventName": "AES_CYCLES",
+ "BriefDescription": "AES Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "78",
+ "EventName": "AES_BLOCKED_FUNCTIONS",
+ "BriefDescription": "AES Blocked Functions",
+ "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "79",
+ "EventName": "AES_BLOCKED_CYCLES",
+ "BriefDescription": "AES Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z13/extended.json b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
new file mode 100644
index 000000000000..9a002b6967f1
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z13/extended.json
@@ -0,0 +1,338 @@
+[
+ {
+ "EventCode": "128",
+ "EventName": "L1D_RO_EXCL_WRITES",
+ "BriefDescription": "L1D Read-only Exclusive Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
+ },
+ {
+ "EventCode": "129",
+ "EventName": "DTLB1_WRITES",
+ "BriefDescription": "DTLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "130",
+ "EventName": "DTLB1_MISSES",
+ "BriefDescription": "DTLB1 Misses",
+ "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
+ },
+ {
+ "EventCode": "131",
+ "EventName": "DTLB1_HPAGE_WRITES",
+ "BriefDescription": "DTLB1 One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page"
+ },
+ {
+ "EventCode": "132",
+ "EventName": "DTLB1_GPAGE_WRITES",
+ "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
+ "PublicDescription": "Counter:132 Name:DTLB1_GPAGE_WRITES A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
+ },
+ {
+ "EventCode": "133",
+ "EventName": "L1D_L2D_SOURCED_WRITES",
+ "BriefDescription": "L1D L2D Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+ },
+ {
+ "EventCode": "134",
+ "EventName": "ITLB1_WRITES",
+ "BriefDescription": "ITLB1 Writes",
+ "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer"
+ },
+ {
+ "EventCode": "135",
+ "EventName": "ITLB1_MISSES",
+ "BriefDescription": "ITLB1 Misses",
+ "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
+ },
+ {
+ "EventCode": "136",
+ "EventName": "L1I_L2I_SOURCED_WRITES",
+ "BriefDescription": "L1I L2I Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+ },
+ {
+ "EventCode": "137",
+ "EventName": "TLB2_PTE_WRITES",
+ "BriefDescription": "TLB2 PTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
+ },
+ {
+ "EventCode": "138",
+ "EventName": "TLB2_CRSTE_HPAGE_WRITES",
+ "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation"
+ },
+ {
+ "EventCode": "139",
+ "EventName": "TLB2_CRSTE_WRITES",
+ "BriefDescription": "TLB2 CRSTE Writes",
+ "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays"
+ },
+ {
+ "EventCode": "140",
+ "EventName": "TX_C_TEND",
+ "BriefDescription": "Completed TEND instructions in constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "141",
+ "EventName": "TX_NC_TEND",
+ "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "143",
+ "EventName": "L1C_TLB1_MISSES",
+ "BriefDescription": "L1C TLB1 Misses",
+ "PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
+ },
+ {
+ "EventCode": "144",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "145",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "146",
+ "EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Node L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
+ },
+ {
+ "EventCode": "147",
+ "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "148",
+ "EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Node L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "149",
+ "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "150",
+ "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "151",
+ "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Drawer L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "152",
+ "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
+ },
+ {
+ "EventCode": "153",
+ "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "154",
+ "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "155",
+ "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
+ },
+ {
+ "EventCode": "156",
+ "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "157",
+ "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "158",
+ "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Node Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory"
+ },
+ {
+ "EventCode": "159",
+ "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
+ },
+ {
+ "EventCode": "160",
+ "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory"
+ },
+ {
+ "EventCode": "161",
+ "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
+ },
+ {
+ "EventCode": "162",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "163",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "164",
+ "EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache"
+ },
+ {
+ "EventCode": "165",
+ "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "166",
+ "EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Node L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "167",
+ "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "168",
+ "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "169",
+ "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Drawer L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "170",
+ "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache"
+ },
+ {
+ "EventCode": "171",
+ "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "172",
+ "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "173",
+ "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache"
+ },
+ {
+ "EventCode": "174",
+ "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "175",
+ "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "176",
+ "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Node Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory"
+ },
+ {
+ "EventCode": "177",
+ "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
+ },
+ {
+ "EventCode": "178",
+ "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory"
+ },
+ {
+ "EventCode": "179",
+ "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory"
+ },
+ {
+ "EventCode": "218",
+ "EventName": "TX_NC_TABORT",
+ "BriefDescription": "Aborted transactions in non-constrained TX mode",
+ "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "219",
+ "EventName": "TX_C_TABORT_NO_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+ },
+ {
+ "EventCode": "220",
+ "EventName": "TX_C_TABORT_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+ },
+ {
+ "EventCode": "448",
+ "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
+ "BriefDescription": "Cycle count with one thread active",
+ "PublicDescription": "Cycle count with one thread active"
+ },
+ {
+ "EventCode": "449",
+ "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
+ "BriefDescription": "Cycle count with two threads active",
+ "PublicDescription": "Cycle count with two threads active"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index c57f8e75fa23..3cff9c64bb85 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -2,3 +2,4 @@ Family-model,Version,Filename,EventType
209[78],1,cf_z10,core
281[78],1,cf_z196,core
282[78],1,cf_zec12,core
+296[45],1,cf_z13,core
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH 8/8] perf vendor events s390: Add JSON files for IBM z14
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (6 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 7/8] perf vendor events s390: Add JSON files for IBM z13 Arnaldo Carvalho de Melo
@ 2018-03-28 18:49 ` Arnaldo Carvalho de Melo
2018-03-29 7:23 ` [GIT PULL 0/8] perf/core improvements and fixes Ingo Molnar
8 siblings, 0 replies; 12+ messages in thread
From: Arnaldo Carvalho de Melo @ 2018-03-28 18:49 UTC (permalink / raw)
To: Ingo Molnar
Cc: linux-kernel, linux-perf-users, Thomas Richter, Heiko Carstens,
Martin Schwidefsky, Arnaldo Carvalho de Melo
From: Thomas Richter <tmricht@linux.vnet.ibm.com>
Add CPU measurement counter facility event description files (json
files) for IBM z14.
Signed-off-by: Thomas Richter <tmricht@linux.vnet.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.vnet.ibm.com>
Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Link: http://lkml.kernel.org/r/20180326082538.2258-5-tmricht@linux.vnet.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/perf/pmu-events/arch/s390/cf_z14/basic.json | 50 ++++
tools/perf/pmu-events/arch/s390/cf_z14/crypto.json | 98 +++++++
.../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++++
tools/perf/pmu-events/arch/s390/mapfile.csv | 1 +
4 files changed, 469 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/basic.json b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
new file mode 100644
index 000000000000..8f653c9d899d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/basic.json
@@ -0,0 +1,50 @@
+[
+ {
+ "EventCode": "0",
+ "EventName": "CPU_CYCLES",
+ "BriefDescription": "CPU Cycles",
+ "PublicDescription": "Cycle Count"
+ },
+ {
+ "EventCode": "1",
+ "EventName": "INSTRUCTIONS",
+ "BriefDescription": "Instructions",
+ "PublicDescription": "Instruction Count"
+ },
+ {
+ "EventCode": "2",
+ "EventName": "L1I_DIR_WRITES",
+ "BriefDescription": "L1I Directory Writes",
+ "PublicDescription": "Level-1 I-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "3",
+ "EventName": "L1I_PENALTY_CYCLES",
+ "BriefDescription": "L1I Penalty Cycles",
+ "PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "4",
+ "EventName": "L1D_DIR_WRITES",
+ "BriefDescription": "L1D Directory Writes",
+ "PublicDescription": "Level-1 D-Cache Directory Write Count"
+ },
+ {
+ "EventCode": "5",
+ "EventName": "L1D_PENALTY_CYCLES",
+ "BriefDescription": "L1D Penalty Cycles",
+ "PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
+ },
+ {
+ "EventCode": "32",
+ "EventName": "PROBLEM_STATE_CPU_CYCLES",
+ "BriefDescription": "Problem-State CPU Cycles",
+ "PublicDescription": "Problem-State Cycle Count"
+ },
+ {
+ "EventCode": "33",
+ "EventName": "PROBLEM_STATE_INSTRUCTIONS",
+ "BriefDescription": "Problem-State Instructions",
+ "PublicDescription": "Problem-State Instruction Count"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
new file mode 100644
index 000000000000..7e5b72492141
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
@@ -0,0 +1,98 @@
+[
+ {
+ "EventCode": "64",
+ "EventName": "PRNG_FUNCTIONS",
+ "BriefDescription": "PRNG Functions",
+ "PublicDescription": "Total number of the PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "65",
+ "EventName": "PRNG_CYCLES",
+ "BriefDescription": "PRNG Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
+ },
+ {
+ "EventCode": "66",
+ "EventName": "PRNG_BLOCKED_FUNCTIONS",
+ "BriefDescription": "PRNG Blocked Functions",
+ "PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "67",
+ "EventName": "PRNG_BLOCKED_CYCLES",
+ "BriefDescription": "PRNG Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "68",
+ "EventName": "SHA_FUNCTIONS",
+ "BriefDescription": "SHA Functions",
+ "PublicDescription": "Total number of SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "69",
+ "EventName": "SHA_CYCLES",
+ "BriefDescription": "SHA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
+ },
+ {
+ "EventCode": "70",
+ "EventName": "SHA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "SHA Blocked Functions",
+ "PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "71",
+ "EventName": "SHA_BLOCKED_CYCLES",
+ "BriefDescription": "SHA Bloced Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "72",
+ "EventName": "DEA_FUNCTIONS",
+ "BriefDescription": "DEA Functions",
+ "PublicDescription": "Total number of the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "73",
+ "EventName": "DEA_CYCLES",
+ "BriefDescription": "DEA Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
+ },
+ {
+ "EventCode": "74",
+ "EventName": "DEA_BLOCKED_FUNCTIONS",
+ "BriefDescription": "DEA Blocked Functions",
+ "PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "75",
+ "EventName": "DEA_BLOCKED_CYCLES",
+ "BriefDescription": "DEA Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "76",
+ "EventName": "AES_FUNCTIONS",
+ "BriefDescription": "AES Functions",
+ "PublicDescription": "Total number of AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "77",
+ "EventName": "AES_CYCLES",
+ "BriefDescription": "AES Cycles",
+ "PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
+ },
+ {
+ "EventCode": "78",
+ "EventName": "AES_BLOCKED_FUNCTIONS",
+ "BriefDescription": "AES Blocked Functions",
+ "PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+ {
+ "EventCode": "79",
+ "EventName": "AES_BLOCKED_CYCLES",
+ "BriefDescription": "AES Blocked Cycles",
+ "PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/cf_z14/extended.json b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
new file mode 100644
index 000000000000..aa4dfb46b65b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/s390/cf_z14/extended.json
@@ -0,0 +1,320 @@
+[
+ {
+ "EventCode": "128",
+ "EventName": "L1D_RO_EXCL_WRITES",
+ "BriefDescription": "L1D Read-only Exclusive Writes",
+ "PublicDescription": "Counter:128 Name:L1D_RO_EXCL_WRITES A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
+ },
+ {
+ "EventCode": "129",
+ "EventName": "DTLB2_WRITES",
+ "BriefDescription": "DTLB2 Writes",
+ "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
+ },
+ {
+ "EventCode": "130",
+ "EventName": "DTLB2_MISSES",
+ "BriefDescription": "DTLB2 Misses",
+ "PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
+ },
+ {
+ "EventCode": "131",
+ "EventName": "DTLB2_HPAGE_WRITES",
+ "BriefDescription": "DTLB2 One-Megabyte Page Writes",
+ "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page or a Last Host Translation was done"
+ },
+ {
+ "EventCode": "132",
+ "EventName": "DTLB2_GPAGE_WRITES",
+ "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
+ "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
+ },
+ {
+ "EventCode": "133",
+ "EventName": "L1D_L2D_SOURCED_WRITES",
+ "BriefDescription": "L1D L2D Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
+ },
+ {
+ "EventCode": "134",
+ "EventName": "ITLB2_WRITES",
+ "BriefDescription": "ITLB2 Writes",
+ "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
+ },
+ {
+ "EventCode": "135",
+ "EventName": "ITLB2_MISSES",
+ "BriefDescription": "ITLB2 Misses",
+ "PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
+ },
+ {
+ "EventCode": "136",
+ "EventName": "L1I_L2I_SOURCED_WRITES",
+ "BriefDescription": "L1I L2I Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
+ },
+ {
+ "EventCode": "137",
+ "EventName": "TLB2_PTE_WRITES",
+ "BriefDescription": "TLB2 PTE Writes",
+ "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
+ },
+ {
+ "EventCode": "138",
+ "EventName": "TLB2_CRSTE_WRITES",
+ "BriefDescription": "TLB2 CRSTE Writes",
+ "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
+ },
+ {
+ "EventCode": "139",
+ "EventName": "TLB2_ENGINES_BUSY",
+ "BriefDescription": "TLB2 Engines Busy",
+ "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
+ },
+ {
+ "EventCode": "140",
+ "EventName": "TX_C_TEND",
+ "BriefDescription": "Completed TEND instructions in constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "141",
+ "EventName": "TX_NC_TEND",
+ "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
+ "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "143",
+ "EventName": "L1C_TLB2_MISSES",
+ "BriefDescription": "L1C TLB2 Misses",
+ "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
+ },
+ {
+ "EventCode": "144",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "145",
+ "EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Chip Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
+ },
+ {
+ "EventCode": "146",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "147",
+ "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Cluster L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
+ },
+ {
+ "EventCode": "148",
+ "EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Cluster Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
+ },
+ {
+ "EventCode": "149",
+ "EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "150",
+ "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "151",
+ "EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
+ },
+ {
+ "EventCode": "152",
+ "EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "153",
+ "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "154",
+ "EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
+ },
+ {
+ "EventCode": "155",
+ "EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "156",
+ "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "157",
+ "EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "158",
+ "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
+ "BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
+ "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
+ },
+ {
+ "EventCode": "162",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "163",
+ "EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Chip Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
+ },
+ {
+ "EventCode": "164",
+ "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "165",
+ "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Cluster L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "166",
+ "EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Cluster Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
+ },
+ {
+ "EventCode": "167",
+ "EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "168",
+ "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "169",
+ "EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
+ },
+ {
+ "EventCode": "170",
+ "EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "171",
+ "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
+ },
+ {
+ "EventCode": "172",
+ "EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
+ },
+ {
+ "EventCode": "173",
+ "EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
+ "BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
+ },
+ {
+ "EventCode": "174",
+ "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "175",
+ "EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
+ "BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
+ "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
+ },
+ {
+ "EventCode": "224",
+ "EventName": "BCD_DFP_EXECUTION_SLOTS",
+ "BriefDescription": "BCD DFP Execution Slots",
+ "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
+ },
+ {
+ "EventCode": "225",
+ "EventName": "VX_BCD_EXECUTION_SLOTS",
+ "BriefDescription": "VX BCD Execution Slots",
+ "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
+ },
+ {
+ "EventCode": "226",
+ "EventName": "DECIMAL_INSTRUCTIONS",
+ "BriefDescription": "Decimal Instructions",
+ "PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
+ },
+ {
+ "EventCode": "232",
+ "EventName": "LAST_HOST_TRANSLATIONS",
+ "BriefDescription": "Last host translation done",
+ "PublicDescription": "Last Host Translation done"
+ },
+ {
+ "EventCode": "243",
+ "EventName": "TX_NC_TABORT",
+ "BriefDescription": "Aborted transactions in non-constrained TX mode",
+ "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
+ },
+ {
+ "EventCode": "244",
+ "EventName": "TX_C_TABORT_NO_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
+ },
+ {
+ "EventCode": "245",
+ "EventName": "TX_C_TABORT_SPECIAL",
+ "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
+ "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
+ },
+ {
+ "EventCode": "448",
+ "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
+ "BriefDescription": "Cycle count with one thread active",
+ "PublicDescription": "Cycle count with one thread active"
+ },
+ {
+ "EventCode": "449",
+ "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
+ "BriefDescription": "Cycle count with two threads active",
+ "PublicDescription": "Cycle count with two threads active"
+ },
+]
diff --git a/tools/perf/pmu-events/arch/s390/mapfile.csv b/tools/perf/pmu-events/arch/s390/mapfile.csv
index 3cff9c64bb85..ca7682748a4b 100644
--- a/tools/perf/pmu-events/arch/s390/mapfile.csv
+++ b/tools/perf/pmu-events/arch/s390/mapfile.csv
@@ -3,3 +3,4 @@ Family-model,Version,Filename,EventType
281[78],1,cf_z196,core
282[78],1,cf_zec12,core
296[45],1,cf_z13,core
+3906,3,cf_z14,core
--
2.14.3
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [GIT PULL 0/8] perf/core improvements and fixes
2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
` (7 preceding siblings ...)
2018-03-28 18:49 ` [PATCH 8/8] perf vendor events s390: Add JSON files for IBM z14 Arnaldo Carvalho de Melo
@ 2018-03-29 7:23 ` Ingo Molnar
8 siblings, 0 replies; 12+ messages in thread
From: Ingo Molnar @ 2018-03-29 7:23 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo
Cc: linux-kernel, linux-perf-users, Adrian Hunter, Alexander Shishkin,
David Ahern, Heiko Carstens, Hendrik Brueckner, Jiri Olsa,
Kan Liang, Martin Schwidefsky, Namhyung Kim, Peter Zijlstra,
Thomas Richter, Wang Nan, Arnaldo Carvalho de Melo
* Arnaldo Carvalho de Melo <acme@kernel.org> wrote:
> Hi Ingo,
>
> Please consider pulling,
>
> - Arnaldo
>
> Test results at the end of this message, as usual.
>
> The following changes since commit 631fe154edb0a37308d0116a0f9b7bba9dca6218:
>
> perf/x86: Update rdpmc_always_available static key to the modern API (2018-03-27 07:53:00 +0200)
>
> are available in the Git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git tags/perf-core-for-mingo-4.17-20180328
>
> for you to fetch changes up to 109d59b900e78834c66657dd4748fcedb9a1fe8d:
>
> perf vendor events s390: Add JSON files for IBM z14 (2018-03-27 13:13:39 -0300)
>
> ----------------------------------------------------------------
> perf/core improvements and fixes:
>
> - Be consistent when checking if a perf_mmap instance had
> its ring buffer unmmaped, fixing segfaults noticed in
> 'perf trace' (Kan Liang, Arnaldo Carvalho de Melo)
>
> - Avoid adding the same option multiple times to the 'diff'
> command in check-headers.sh (Jiri Olsa)
>
> - Add vendor event files (JSON format) to various IBM
> s390 models (z10EC, z10BC, z196, zEC12, zBC12, z13
> and z14) (Thomas Richter)
>
> Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
>
> ----------------------------------------------------------------
> Arnaldo Carvalho de Melo (1):
> perf mmap: Be consistent when checking for an unmaped ring buffer
>
> Jiri Olsa (1):
> perf build: Fix check-headers.sh opts assignment
>
> Kan Liang (1):
> perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done()
>
> Thomas Richter (5):
> perf vendor events s390: Add JSON files for IBM z10EC z10BC
> perf vendor events s390: Add JSON files for IBM z196
> perf vendor events s390: Add JSON files for IBM zEC12 zBC12
> perf vendor events s390: Add JSON files for IBM z13
> perf vendor events s390: Add JSON files for IBM z14
>
> tools/perf/check-headers.sh | 1 +
> tools/perf/pmu-events/arch/s390/cf_z10/basic.json | 74 +++++
> tools/perf/pmu-events/arch/s390/cf_z10/crypto.json | 98 ++++++
> .../perf/pmu-events/arch/s390/cf_z10/extended.json | 110 +++++++
> tools/perf/pmu-events/arch/s390/cf_z13/basic.json | 74 +++++
> tools/perf/pmu-events/arch/s390/cf_z13/crypto.json | 98 ++++++
> .../perf/pmu-events/arch/s390/cf_z13/extended.json | 338 +++++++++++++++++++++
> tools/perf/pmu-events/arch/s390/cf_z14/basic.json | 50 +++
> tools/perf/pmu-events/arch/s390/cf_z14/crypto.json | 98 ++++++
> .../perf/pmu-events/arch/s390/cf_z14/extended.json | 320 +++++++++++++++++++
> tools/perf/pmu-events/arch/s390/cf_z196/basic.json | 74 +++++
> .../perf/pmu-events/arch/s390/cf_z196/crypto.json | 98 ++++++
> .../pmu-events/arch/s390/cf_z196/extended.json | 146 +++++++++
> .../perf/pmu-events/arch/s390/cf_zec12/basic.json | 74 +++++
> .../perf/pmu-events/arch/s390/cf_zec12/crypto.json | 98 ++++++
> .../pmu-events/arch/s390/cf_zec12/extended.json | 212 +++++++++++++
> tools/perf/pmu-events/arch/s390/mapfile.csv | 6 +
> tools/perf/util/mmap.c | 19 +-
> 18 files changed, 1987 insertions(+), 1 deletion(-)
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/basic.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/crypto.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z10/extended.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/basic.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/crypto.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z13/extended.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/basic.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/crypto.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z14/extended.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/basic.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/crypto.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_z196/extended.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/basic.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/crypto.json
> create mode 100644 tools/perf/pmu-events/arch/s390/cf_zec12/extended.json
> create mode 100644 tools/perf/pmu-events/arch/s390/mapfile.csv
Pulled, thanks a lot Arnaldo!
Ingo
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2018-03-29 7:23 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
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2018-03-28 18:49 [GIT PULL 0/8] perf/core improvements and fixes Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 1/8] perf build: Fix check-headers.sh opts assignment Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 2/8] perf mmap: Fix accessing unmapped mmap in perf_mmap__read_done() Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 3/8] perf mmap: Be consistent when checking for an unmaped ring buffer Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 4/8] perf vendor events s390: Add JSON files for IBM z10EC z10BC Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 5/8] perf vendor events s390: Add JSON files for IBM z196 Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 6/8] perf vendor events s390: Add JSON files for IBM zEC12 zBC12 Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 7/8] perf vendor events s390: Add JSON files for IBM z13 Arnaldo Carvalho de Melo
2018-03-28 18:49 ` [PATCH 8/8] perf vendor events s390: Add JSON files for IBM z14 Arnaldo Carvalho de Melo
2018-03-29 7:23 ` [GIT PULL 0/8] perf/core improvements and fixes Ingo Molnar
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2017-10-03 12:55 Arnaldo Carvalho de Melo
2017-10-03 16:38 ` Ingo Molnar
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