From: Nikita Shubin <nikita.shubin@maquefel.me>
To: Atish Patra <atish.patra@wdc.com>
Cc: linux-kernel@vger.kernel.org,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anup Patel <anup.patel@wdc.com>, Ard Biesheuvel <ardb@kernel.org>,
"Darrick J. Wong" <djwong@kernel.org>,
devicetree@vger.kernel.org, Guo Ren <guoren@linux.alibaba.com>,
Heinrich Schuchardt <xypron.glpk@gmx.de>,
Jiri Olsa <jolsa@redhat.com>, John Garry <john.garry@huawei.com>,
Jonathan Corbet <corbet@lwn.net>,
linux-doc@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
Nick Kossifidis <mick@ics.forth.gr>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Vincent Chen <vincent.chen@sifive.com>
Subject: Re: [v3 00/10] Improve RISC-V Perf support using SBI PMU and sscofpmf extension
Date: Tue, 5 Oct 2021 12:17:44 +0300 [thread overview]
Message-ID: <20211005121744.728385be@redslave.neermore.group> (raw)
In-Reply-To: <20210910192757.2309100-1-atish.patra@wdc.com>
On Fri, 10 Sep 2021 12:27:47 -0700
Atish Patra <atish.patra@wdc.com> wrote:
Hello Atish,
> Perf stat:
> =========
>
> [root@fedora-riscv riscv]# perf stat -e r8000000000000005 -e
> r8000000000000007 -e r8000000000000006 -e r0000000000020002 -e
> r0000000000020004 -e branch-misses -e cache-misses -e
> dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -e cycles
> -e instructions ./hackbench -pipe 15 process Running with 15*40 (==
> 600) tasks. Time: 6.578
>
> Performance counter stats for './hackbench -pipe 15 process':
>
> 6,491 r8000000000000005 (52.59%) -->
> SBI_PMU_FW_SET_TIMER 20,433 r8000000000000007 (60.74%) -->
> SBI_PMU_FW_IPI_RECVD 21,271 r8000000000000006 (68.71%) -->
> SBI_PMU_FW_IPI_SENT 0 r0000000000020002 (76.55%)
> <not counted> r0000000000020004 (0.00%)
> <not counted> branch-misses (0.00%)
> <not counted> cache-misses (0.00%)
> 57,537,853 dTLB-load-misses (9.49%)
> 2,821,147 dTLB-store-misses (18.64%)
> 52,928,130 iTLB-load-misses (27.53%)
> 89,521,791,110 cycles (36.08%)
> 90,678,132,464 instructions # 1.01 insn per cycle
> (44.44%)
>
> 6.975908032 seconds time elapsed
>
> 3.130950000 seconds user
> 24.353310000 seconds sys
>
Tested your patch series with qemu and got results as expected:
perf stat -e r8000000000000005 -e r8000000000000007 \
-e r8000000000000006 -e r0000000000020002 -e r0000000000020004 -e
branch-misses \ -e cache-misses -e dTLB-load-misses -e
dTLB-store-misses -e iTLB-load-misses \ -e cycles -e instructions
./hackbench -pipe 15 process
Running with 15*40 (== 600) tasks.nch -pipe 15 process
Time: 20.027
Performance counter stats for './hackbench -pipe 15 process':
4896 r8000000000000005
(53.34%) 0 r8000000000000007
(61.20%) 0
r8000000000000006
(68.88%) 0 r0000000000020002
(76.53%) <not counted>
r0000000000020004
(0.00%) <not counted> branch-misses
(0.00%) <not counted>
cache-misses
(0.00%) 48414917 dTLB-load-misses
(9.87%) 2427413
dTLB-store-misses
(19.43%) 46958092 iTLB-load-misses
(28.58%) 69245163600
cycles
(37.09%) 70334279943 instructions #
1.02 insn per cycle (45.24%)
20.895871900 seconds time elapsed
2.724942000 seconds user
18.126277000 seconds sys
perf top/record also works.
Tested-by: Nikita Shubin <n.shubin@yadro.com>
Yours,
Nikita Shubin
next prev parent reply other threads:[~2021-10-05 9:24 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-10 19:27 [v3 00/10] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2021-09-10 19:27 ` [v3 01/10] RISC-V: Remove the current perf implementation Atish Patra
[not found] ` <238571632287002@mail.yandex.ru>
2021-09-22 5:25 ` Nikita Shubin
2021-09-10 19:27 ` [v3 02/10] RISC-V: Add CSR encodings for all HPMCOUNTERS Atish Patra
2021-09-10 19:27 ` [v3 03/10] RISC-V: Add a perf core library for pmu drivers Atish Patra
2021-09-10 19:27 ` [v3 04/10] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2021-09-10 19:27 ` [v3 05/10] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2021-09-10 19:27 ` [v3 06/10] dt-binding: pmu: Add RISC-V PMU DT bindings Atish Patra
2021-09-13 12:18 ` Rob Herring
2021-09-14 15:50 ` Rob Herring
2021-09-10 19:27 ` [v3 07/10] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2021-09-10 19:27 ` [v3 08/10] RISC-V: Add interrupt support for perf Atish Patra
2021-09-10 19:27 ` [v3 09/10] Documentation: riscv: Remove the old documentation Atish Patra
2021-09-10 19:27 ` [v3 10/10] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2021-10-04 18:20 ` [v3 00/10] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Palmer Dabbelt
2021-10-06 18:27 ` Atish Patra
2021-10-05 9:17 ` Nikita Shubin [this message]
2021-10-06 18:28 ` Atish Patra
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