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charset=us-ascii Content-Disposition: inline In-Reply-To: <20211017120546.GB130233@leoy-ThinkPad-X240s> Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org On Sun, Oct 17, 2021 at 08:05:46PM +0800, Leo Yan wrote: [...] > To allow arm_spe_buffer_has_wrapped() to work properly, I think we > need to clean up the top 8 bytes of the AUX buffer in Arm SPE driver > when start the PMU event (please note, this change has an assumption > that is meantioned in another email that suggests to remove redundant > PERF_RECORD_AUX events so the function arm_spe_perf_aux_output_begin() > is invoked only once when start PMU event, so we can use the top 8 > bytes in AUX buffer to indicate trace is wrap around or not). > > > diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c > index d44bcc29d99c..eb35f85d0efb 100644 > --- a/drivers/perf/arm_spe_pmu.c > +++ b/drivers/perf/arm_spe_pmu.c > @@ -493,6 +493,16 @@ static void arm_spe_perf_aux_output_begin(struct perf_output_handle *handle, > if (limit) > limit |= BIT(SYS_PMBLIMITR_EL1_E_SHIFT); > > + /* > + * Cleanup the top 8 bytes for snapshot mode; these 8 bytes are > + * used to indicate if trace data is wrap around if they are not > + * zero. > + */ > + if (buf->snapshot) { > + void *tail = buf->base + (buf->nr_pages << PAGE_SHIFT) - 8; > + memset(tail, 0x0, 8); Here need to add below code for flushing data cache: flush_dcache_range((unsigned long)tail, (unsigned long)tail+8); Sorry for spamming. Leo > + } > + > limit += (u64)buf->base; > base = (u64)buf->base + PERF_IDX2OFF(handle->head, buf); > write_sysreg_s(base, SYS_PMBPTR_EL1);