From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D06C433F5 for ; Tue, 4 Jan 2022 13:57:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232631AbiADN5K (ORCPT ); Tue, 4 Jan 2022 08:57:10 -0500 Received: from ams.source.kernel.org ([145.40.68.75]:55482 "EHLO ams.source.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229655AbiADN5J (ORCPT ); Tue, 4 Jan 2022 08:57:09 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 16BA4B810B3; Tue, 4 Jan 2022 13:57:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 47123C36AED; Tue, 4 Jan 2022 13:57:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1641304626; bh=OZ0f7tUVt0pRqeuyYIwF4uJjwkRgSIkddO3+gxXzU28=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=XPTU3Ic2LMotntRgbC7j3XdoRwKaXQd3itYu9WeU6v5J4oCfm6dF1o1MFDUCyLshj 7k335DQFq5lyvm3hWVZLxHvwwr4bGiuvzgwxEjTwjl/QZ395arVRRET3BDh84lZN/j Zkey+mFkYaqwBOkKXUWrgXUlxjCc4hh0PxjHCOqtWOnO8FlWpVtt9iz1FIlqQn6UR8 JNp4NvwdkNAHuAbQx5h2wCVBz8gBkixppBOIcwbPv7dLcb2mF1RZYMYf1DyM9z1vo4 lXlq/dhdcSBsy8hfXVuvKT8DvJCNvJJp6YLP6yZPHHQRz6I6p+d3HtiaufgZ7l5KNu kIadDSUcXpQow== Date: Tue, 4 Jan 2022 13:56:59 +0000 From: Will Deacon To: Geert Uytterhoeven Cc: Rob Herring , Mark Rutland , Peter Zijlstra , Vince Weaver , Jonathan Corbet , Catalin Marinas , Ingo Molnar , Arnaldo Carvalho de Melo , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Thomas Gleixner , Borislav Petkov , the arch/x86 maintainers , "H. Peter Anvin" , Linux Kernel Mailing List , Linux ARM , linux-perf-users@vger.kernel.org, Linux-Renesas Subject: Re: [PATCH v13 3/5] arm64: perf: Add userspace counter access disable switch Message-ID: <20220104135658.GC1827@willie-the-truck> References: <20211208201124.310740-1-robh@kernel.org> <20211208201124.310740-4-robh@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Hi Geert, On Tue, Dec 28, 2021 at 12:07:02PM +0100, Geert Uytterhoeven wrote: > On Wed, Dec 8, 2021 at 9:19 PM Rob Herring wrote: > > Like x86, some users may want to disable userspace PMU counter > > altogether. Add a sysctl 'perf_user_access' file to control userspace > > counter access. The default is '0' which is disabled. Writing '1' > > enables access. > > > > Note that x86 supports globally enabling user access by writing '2' to > > /sys/bus/event_source/devices/cpu/rdpmc. As there's not existing > > userspace support to worry about, this shouldn't be necessary for Arm. > > It could be added later if the need arises. > > Thanks for your patch, which is now commit e2012600810c9ded ("arm64: > perf: Add userspace counter access disable switch") in arm64/for-next/core. > > This is causing two issues on Renesas Salvator-XS with R-Car H3. > One during kernel boot: > > hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 > counters available > +sysctl duplicate entry: /kernel//perf_user_access > +CPU: 0 PID: 1 Comm: swapper/0 Not tainted > 5.16.0-rc3-arm64-renesas-00003-ge2012600810c #1420 > +Hardware name: Renesas Salvator-X 2nd version board based on r8a77951 (DT) > +Call trace: > + dump_backtrace+0x0/0x190 > + show_stack+0x14/0x20 > + dump_stack_lvl+0x88/0xb0 > + dump_stack+0x14/0x2c > + __register_sysctl_table+0x384/0x818 > + register_sysctl+0x20/0x28 > + armv8_pmu_init.constprop.0+0x118/0x150 > + armv8_a57_pmu_init+0x1c/0x28 > + arm_pmu_device_probe+0x1b4/0x558 > + armv8_pmu_device_probe+0x18/0x20 > + platform_probe+0x64/0xd0 > + really_probe+0xb4/0x2f8 > + __driver_probe_device+0x74/0xd8 > + driver_probe_device+0x3c/0xe0 > + __driver_attach+0x80/0x110 > + bus_for_each_dev+0x6c/0xc0 > + driver_attach+0x20/0x28 > + bus_add_driver+0x138/0x1e0 > + driver_register+0x60/0x110 > + __platform_driver_register+0x24/0x30 > + armv8_pmu_driver_init+0x18/0x20 > + do_one_initcall+0x15c/0x31c > + kernel_init_freeable+0x2f0/0x354 > + kernel_init+0x20/0x120 > + ret_from_fork+0x10/0x20 > hw perfevents: enabled with armv8_cortex_a57 PMU driver, 7 > counters available > > Presumably the same entry is added twice, once for the A53 PMU, > and a second time for the A57 PMU? Looks like it, and perhaps that's also what is confusing systemd? Rob -- how come you didn't see this during your testing? Anywho, please can you try the untested diff below? Thanks, Will --->8 diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 81cc9f0e718a..639f632aaa66 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -1214,6 +1214,14 @@ static struct ctl_table armv8_pmu_sysctl_table[] = { { } }; +static void armv8_pmu_register_sysctl_table(void) +{ + static u32 tbl_registered = 0; + + if (!cmpxchg_relaxed(&tbl_registered, 0, 1)) + register_sysctl("kernel", armv8_pmu_sysctl_table); +} + static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, int (*map_event)(struct perf_event *event), const struct attribute_group *events, @@ -1248,8 +1256,7 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name, cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_CAPS] = caps ? caps : &armv8_pmuv3_caps_attr_group; - register_sysctl("kernel", armv8_pmu_sysctl_table); - + armv8_pmu_register_sysctl_table(); return 0; }