From: Ali Saidi <alisaidi@amazon.com>
To: <linux-kernel@vger.kernel.org>,
<linux-perf-users@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>, <german.gomez@arm.com>,
<leo.yan@linaro.org>
Cc: <alisaidi@amazon.com>, <benh@kernel.crashing.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
"Arnaldo Carvalho de Melo" <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
John Garry <john.garry@huawei.com>,
"Will Deacon" <will@kernel.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
"James Clark" <james.clark@arm.com>,
Andrew Kilroy <andrew.kilroy@arm.com>,
Jin Yao <yao.jin@linux.intel.com>,
Kajol Jain <kjain@linux.ibm.com>,
Li Huafei <lihuafei1@huawei.com>
Subject: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used
Date: Mon, 21 Feb 2022 22:48:00 +0000 [thread overview]
Message-ID: <20220221224807.18172-2-alisaidi@amazon.com> (raw)
In-Reply-To: <20220221224807.18172-1-alisaidi@amazon.com>
Current code only support HITM statistics for last level cache (LLC)
when mem_lvl encodes the level. On existing Arm64 machines there are as
many as four levels cache and this change supports decoding l1, l2, and
llc hits from the mem_lvl_num data. Given that the mem_lvl namespace is
being deprecated take this opportunity to encode the neoverse data into
mem_lvl_num.
For loads that hit in a the LLC snoop filter and are fullfilled from a
higher level cache, it's not usually clear what the true level of the
cache the data came from (i.e. a transfer from a core could come from
it's L1 or L2). Instead of making an assumption of where the line came
from, add support for incrementing HITM if the source is CACHE_ANY.
Since other architectures don't seem to populate the mem_lvl_num field
here there shouldn't be a change in functionality.
Signed-off-by: Ali Saidi <alisaidi@amazon.com>
---
tools/perf/util/mem-events.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/mem-events.c b/tools/perf/util/mem-events.c
index ed0ab838bcc5..6c3fd4aac7ae 100644
--- a/tools/perf/util/mem-events.c
+++ b/tools/perf/util/mem-events.c
@@ -485,6 +485,7 @@ int c2c_decode_stats(struct c2c_stats *stats, struct mem_info *mi)
u64 daddr = mi->daddr.addr;
u64 op = data_src->mem_op;
u64 lvl = data_src->mem_lvl;
+ u64 lnum = data_src->mem_lvl_num;
u64 snoop = data_src->mem_snoop;
u64 lock = data_src->mem_lock;
u64 blk = data_src->mem_blk;
@@ -527,16 +528,18 @@ do { \
if (lvl & P(LVL, UNC)) stats->ld_uncache++;
if (lvl & P(LVL, IO)) stats->ld_io++;
if (lvl & P(LVL, LFB)) stats->ld_fbhit++;
- if (lvl & P(LVL, L1 )) stats->ld_l1hit++;
- if (lvl & P(LVL, L2 )) stats->ld_l2hit++;
- if (lvl & P(LVL, L3 )) {
+ if (lvl & P(LVL, L1) || lnum == P(LVLNUM, L1))
+ stats->ld_l1hit++;
+ if (lvl & P(LVL, L2) || lnum == P(LVLNUM, L2))
+ stats->ld_l2hit++;
+ if (lvl & P(LVL, L3) || lnum == P(LVLNUM, L4)) {
if (snoop & P(SNOOP, HITM))
HITM_INC(lcl_hitm);
else
stats->ld_llchit++;
}
- if (lvl & P(LVL, LOC_RAM)) {
+ if (lvl & P(LVL, LOC_RAM) || lnum == P(LVLNUM, RAM)) {
stats->lcl_dram++;
if (snoop & P(SNOOP, HIT))
stats->ld_shared++;
@@ -564,6 +567,9 @@ do { \
HITM_INC(rmt_hitm);
}
+ if (lnum == P(LVLNUM, ANY_CACHE) && snoop & P(SNOOP, HITM))
+ HITM_INC(lcl_hitm);
+
if ((lvl & P(LVL, MISS)))
stats->ld_miss++;
--
2.32.0
next prev parent reply other threads:[~2022-02-21 22:48 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 22:47 [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores Ali Saidi
2022-02-21 22:48 ` Ali Saidi [this message]
2022-03-02 15:39 ` [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used German Gomez
2022-03-13 12:44 ` Leo Yan
2022-03-13 19:19 ` Ali Saidi
2022-03-14 6:33 ` Leo Yan
2022-03-14 18:00 ` German Gomez
2022-03-14 18:37 ` Ali Saidi
2022-03-15 18:44 ` German Gomez
2022-03-16 11:43 ` German Gomez
2022-03-16 12:42 ` Leo Yan
2022-03-16 15:10 ` German Gomez
2022-03-02 11:59 ` [PATCH v2 1/2] perf arm-spe: Use SPE data source for neoverse cores German Gomez
2022-03-13 11:46 ` Leo Yan
2022-03-13 19:06 ` Ali Saidi
2022-03-14 4:05 ` Leo Yan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220221224807.18172-2-alisaidi@amazon.com \
--to=alisaidi@amazon.com \
--cc=acme@kernel.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=andrew.kilroy@arm.com \
--cc=benh@kernel.crashing.org \
--cc=german.gomez@arm.com \
--cc=james.clark@arm.com \
--cc=john.garry@huawei.com \
--cc=jolsa@redhat.com \
--cc=kjain@linux.ibm.com \
--cc=leo.yan@linaro.org \
--cc=lihuafei1@huawei.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=mathieu.poirier@linaro.org \
--cc=mingo@redhat.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=will@kernel.org \
--cc=yao.jin@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).