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From: Leo Yan <leo.yan@linaro.org>
To: German Gomez <german.gomez@arm.com>
Cc: Ali Saidi <alisaidi@amazon.com>,
	Nick.Forrington@arm.com, acme@kernel.org,
	alexander.shishkin@linux.intel.com, andrew.kilroy@arm.com,
	benh@kernel.crashing.org, james.clark@arm.com,
	john.garry@huawei.com, jolsa@kernel.org, kjain@linux.ibm.com,
	lihuafei1@huawei.com, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
	mark.rutland@arm.com, mathieu.poirier@linaro.org,
	mingo@redhat.com, namhyung@kernel.org, peterz@infradead.org,
	will@kernel.org
Subject: Re: [PATCH v4 2/4] perf arm-spe: Use SPE data source for neoverse cores
Date: Thu, 31 Mar 2022 20:44:25 +0800	[thread overview]
Message-ID: <20220331124425.GB1704284@leoy-ThinkPad-X240s> (raw)
In-Reply-To: <4710b4b2-5dcd-00a4-3976-1bd5340f401d@arm.com>

On Thu, Mar 31, 2022 at 01:28:58PM +0100, German Gomez wrote:
> Hi all,
> 
> It seems I gave the Review tags a bit too early this time. Apologies for
> the inconvenience. Indeed there was more interesting discussions to be
> had :)
> 
> (Probably best to remove by tags for the next re-spin)

Now worries, German.  Your review and testing are very helpful :)

> On 29/03/2022 15:32, Ali Saidi wrote:
> > [...]
> >
> >> I still think we should consider to extend the memory levels to
> >> demonstrate clear momory hierarchy on Arm archs, I personally like the
> >> definitions for "PEER_CORE", "LCL_CLSTR", "PEER_CLSTR" and "SYS_CACHE",
> >> though these cache levels are not precise like L1/L2/L3 levels, they can
> >> help us to map very well for the cache topology on Arm archs and without
> >> any confusion.  We could take this as an enhancement if you don't want
> >> to bother the current patch set's upstreaming.
> > I'd like to do this in a separate patch, but I have one other proposal. The
> > Neoverse cores L2 is strictly inclusive of the L1, so even if it's in the L1,
> > it's also in the L2. Given that the Graviton systems and afaik the Ampere
> > systems don't have any cache between the L2 and the SLC, thus anything from
> > PEER_CORE, LCL_CLSTR, or PEER_CLSTR would hit in the L2, perhaps we
> > should just set L2 for these cases? German, are you good with this for now? 
> 
> Sorry for the delay. I'd like to also check this with someone. I'll try
> to get back asap. In the meantime, if this approach is also OK with Leo,
> I think it would be fine by me.

Thanks for the checking internally.  Let me just bring up my another
thinking (sorry that my suggestion is float): another choice is we set
ANY_CACHE as cache level if we are not certain the cache level, and
extend snoop field to indicate the snooping logics, like:

  PERF_MEM_SNOOP_PEER_CORE
  PERF_MEM_SNOOP_LCL_CLSTR
  PERF_MEM_SNOOP_PEER_CLSTR

Seems to me, we doing this is not only for cache level, it's more
important for users to know the variant cost for involving different
snooping logics.

Thanks,
Leo

  reply	other threads:[~2022-03-31 12:44 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-24 18:33 [PATCH v4 0/4] perf: arm-spe: Decode SPE source and use for perf c2c Ali Saidi
2022-03-24 18:33 ` [PATCH v4 1/4] tools: arm64: Import cputype.h Ali Saidi
2022-03-25 18:39   ` Arnaldo Carvalho de Melo
2022-03-25 18:58     ` Ali Saidi
2022-03-25 19:42     ` Arnaldo Carvalho de Melo
2022-03-26  5:49       ` Leo Yan
2022-03-26 13:59         ` Arnaldo Carvalho de Melo
2022-03-24 18:33 ` [PATCH v4 2/4] perf arm-spe: Use SPE data source for neoverse cores Ali Saidi
2022-03-26 13:47   ` Leo Yan
2022-03-26 13:52     ` Arnaldo Carvalho de Melo
2022-03-26 13:56       ` Leo Yan
2022-03-26 14:04         ` Arnaldo Carvalho de Melo
2022-03-26 19:43     ` Ali Saidi
2022-03-27  9:09       ` Leo Yan
2022-03-28  3:08       ` Ali Saidi
2022-03-28 13:05         ` Leo Yan
2022-03-29 13:34           ` Shuai Xue
2022-03-29 14:32           ` Ali Saidi
2022-03-31 12:19             ` Leo Yan
2022-03-31 12:28             ` German Gomez
2022-03-31 12:44               ` Leo Yan [this message]
2022-04-03 20:33                 ` Ali Saidi
2022-04-04 15:12                   ` Leo Yan
2022-04-06 21:00                     ` Ali Saidi
2022-04-08  1:06                       ` Leo Yan
2022-04-07 15:24                 ` German Gomez
2022-04-08  1:18                   ` Leo Yan
2022-03-24 18:33 ` [PATCH v4 3/4] perf mem: Support mem_lvl_num in c2c command Ali Saidi
2022-03-26 13:54   ` Arnaldo Carvalho de Melo
2022-03-24 18:33 ` [PATCH v4 4/4] perf mem: Support HITM for when mem_lvl_num is any Ali Saidi
2022-03-26  6:23   ` Leo Yan
2022-03-26 13:30     ` Arnaldo Carvalho de Melo
2022-03-26 19:14     ` Ali Saidi

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