From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4E5D5C433F5 for ; Thu, 14 Apr 2022 12:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242789AbiDNMew (ORCPT ); Thu, 14 Apr 2022 08:34:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243424AbiDNMet (ORCPT ); Thu, 14 Apr 2022 08:34:49 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0320390262 for ; Thu, 14 Apr 2022 05:32:18 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id h23-20020a17090a051700b001c9c1dd3acbso5523668pjh.3 for ; Thu, 14 Apr 2022 05:32:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Lb2k1BEpSa/+z3XM1HtbDM6QVDJOM+So55d/9ulxPRs=; b=zXucu3uxOuHlgBIeFHXTZQcT0f1Nuj2wADtF8qNjEXDePKfd+pTSETelEAYNVGGNqX cSNT0kjY+IZpN4B2azMgW2RVYC4oSo3VKi8nuBDzDfMTMVfzo6/LE1A09jYRYZeibCv+ C2sP2CL8XuyNyF5b3tt4E+w3JLurTe6nyqV4xnvVHw3q1LCBhtj2AT5ggSX6ked/ABq5 D7shBoM4tTHCpbzmYwilmV14zXLYn/gNKV5PTHSQ7bHjRrnhzjLJ7NJTyCm0TQHvU0MG 6x/1dVPvbCIYfWS4Z0gseji7+oynCbJzF34yLOKo+OjQSbpbCY2KwDmIY3MDsLRdXFrx KN3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=Lb2k1BEpSa/+z3XM1HtbDM6QVDJOM+So55d/9ulxPRs=; b=AgOh/TfZZxYkX+PhBL7l3piOc+Vcvfe8qGi252fInifQjEXVn3z5vRMpfDYhviVNRb EViUE1Xn3lzQINTZlOXmAYdAtfRSFaW1JvaPpFc1o6/cRj0A1CHngX+TCCWdMJZ+6g6v f5JM+WBMMaWsHbiVWB8kJo5G87tDPBu+Gyeg088r0kjDh9kNYEkesN7UyOZZKRlwWkhR kAJk/3B5j8wUAMgcO37WOw434VPJlYLSjImCfvWw4S198RmU98QvZKyirHYt3mSk7p/z Q6fruLRpYLRK9wqBG4AJtNaNC4/X7LcAExfl8h6UgawghUgndzGfkEdC+g63l16EUCJQ CNcQ== X-Gm-Message-State: AOAM531hVRGPUBIckZtb6xAhMQvd6rQ9zwrbXlklEy+zBCES10sc+gH1 AZ+HjVjXojrQZyzDRr7TpKtaHQ== X-Google-Smtp-Source: ABdhPJxG+RZpvYQH/Y35Vaw1qIbgIm9XNnhKiFxumxGNw7owul1/6rThV1N9MNc3Yq6dBawxaJONWQ== X-Received: by 2002:a17:90a:dd46:b0:1b8:8:7303 with SMTP id u6-20020a17090add4600b001b800087303mr4035808pjv.197.1649939537353; Thu, 14 Apr 2022 05:32:17 -0700 (PDT) Received: from localhost.localdomain ([134.195.101.46]) by smtp.gmail.com with ESMTPSA id t184-20020a625fc1000000b004fa3bd9bef0sm2160580pfb.110.2022.04.14.05.32.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Apr 2022 05:32:16 -0700 (PDT) From: Leo Yan To: Arnaldo Carvalho de Melo , Peter Zijlstra , Ingo Molnar , Mark Rutland , Alexander Shishkin , Jiri Olsa , Namhyung Kim , Ravi Bangoria , James Clark , German Gomez , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Leo Yan Subject: [PATCH v3] perf report: Set PERF_SAMPLE_DATA_SRC bit for Arm SPE event Date: Thu, 14 Apr 2022 20:32:01 +0800 Message-Id: <20220414123201.842754-1-leo.yan@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Since commit bb30acae4c4d ("perf report: Bail out --mem-mode if mem info is not available") "perf mem report" and "perf report --mem-mode" don't report result if the PERF_SAMPLE_DATA_SRC bit is missed in sample type. The commit ffab48705205 ("perf: arm-spe: Fix perf report --mem-mode") partially fixes the issue. It adds PERF_SAMPLE_DATA_SRC bit for Arm SPE event, this allows the perf data file generated by kernel v5.18-rc1 or later version can be reported properly. On the other hand, perf tool still fails to be backward compatibility for a data file recorded by an older version's perf which contains Arm SPE trace data. This patch is a workaround in reporting phase, when detects ARM SPE PMU event and without PERF_SAMPLE_DATA_SRC bit, it will force to set the bit in the sample type and give a warning info. Fixes: bb30acae4c4d ("perf report: Bail out --mem-mode if mem info is not available") Signed-off-by: Leo Yan Tested-by: German Gomez Reviewed-by: James Clark --- v3: Remove warning log, add James' review tag. v2: Change event name from "arm_spe_" to "arm_spe"; Add German's test tag. tools/perf/builtin-report.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index 1ad75c7ba074..afe4a5539ecc 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -353,6 +353,7 @@ static int report__setup_sample_type(struct report *rep) struct perf_session *session = rep->session; u64 sample_type = evlist__combined_sample_type(session->evlist); bool is_pipe = perf_data__is_pipe(session->data); + struct evsel *evsel; if (session->itrace_synth_opts->callchain || session->itrace_synth_opts->add_callchain || @@ -407,6 +408,19 @@ static int report__setup_sample_type(struct report *rep) } if (sort__mode == SORT_MODE__MEMORY) { + /* + * FIXUP: prior to kernel 5.18, Arm SPE missed to set + * PERF_SAMPLE_DATA_SRC bit in sample type. For backward + * compatibility, set the bit if it's an old perf data file. + */ + evlist__for_each_entry(session->evlist, evsel) { + if (strstr(evsel->name, "arm_spe") && + !(sample_type & PERF_SAMPLE_DATA_SRC)) { + evsel->core.attr.sample_type |= PERF_SAMPLE_DATA_SRC; + sample_type |= PERF_SAMPLE_DATA_SRC; + } + } + if (!is_pipe && !(sample_type & PERF_SAMPLE_DATA_SRC)) { ui__error("Selected --mem-mode but no mem data. " "Did you call perf record without -d?\n"); -- 2.25.1