[PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf

[PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf

[Nikita Shubin]

From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>

This patch creates the header.c file for the risc-v architecture and introduces support for
PMU identification through sysfs.
It is now possible to configure pmu-events in risc-v.

Depends on patch [1], that introduces the id sysfs file.

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
[Nikita: replaced soc:pmu to riscv-pmu/id]
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Tested-by: Nikita Shubin <n.shubin@yadro.com>
---
v2->v3:
- Change 'soc/soc:pmu/id' to 'riscv-pmu/id'
---
 drivers/perf/riscv_pmu.c            | 18 ++++++++
 tools/perf/arch/riscv/util/Build    |  1 +
 tools/perf/arch/riscv/util/header.c | 66 +++++++++++++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 tools/perf/arch/riscv/util/header.c

diff --git a/drivers/perf/riscv_pmu.c b/drivers/perf/riscv_pmu.c
index b2b8d2074ed0..d1aa4e0e527f 100644
--- a/drivers/perf/riscv_pmu.c
+++ b/drivers/perf/riscv_pmu.c
@@ -17,6 +17,23 @@
 
 #include <asm/sbi.h>
 
+PMU_FORMAT_ATTR(event, "config:0-63");
+
+static struct attribute *riscv_arch_formats_attr[] = {
+	&format_attr_event.attr,
+	NULL,
+};
+
+static struct attribute_group riscv_pmu_format_group = {
+	.name = "format",
+	.attrs = riscv_arch_formats_attr,
+};
+
+static const struct attribute_group *riscv_pmu_attr_groups[] = {
+	&riscv_pmu_format_group,
+	NULL,
+};
+
 static unsigned long csr_read_num(int csr_num)
 {
 #define switchcase_csr_read(__csr_num, __val)		{\
@@ -307,6 +324,7 @@ struct riscv_pmu *riscv_pmu_alloc(void)
 			cpuc->events[i] = NULL;
 	}
 	pmu->pmu = (struct pmu) {
+		.attr_groups	= riscv_pmu_attr_groups,
 		.event_init	= riscv_pmu_event_init,
 		.add		= riscv_pmu_add,
 		.del		= riscv_pmu_del,
diff --git a/tools/perf/arch/riscv/util/Build b/tools/perf/arch/riscv/util/Build
index 7d3050134ae0..603dbb5ae4dc 100644
--- a/tools/perf/arch/riscv/util/Build
+++ b/tools/perf/arch/riscv/util/Build
@@ -1,4 +1,5 @@
 perf-y += perf_regs.o
+perf-y += header.o
 
 perf-$(CONFIG_DWARF) += dwarf-regs.o
 perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o
diff --git a/tools/perf/arch/riscv/util/header.c b/tools/perf/arch/riscv/util/header.c
new file mode 100644
index 000000000000..98d40b87c9f3
--- /dev/null
+++ b/tools/perf/arch/riscv/util/header.c
@@ -0,0 +1,66 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include <api/fs/fs.h>
+#include <errno.h>
+#include "../../util/debug.h"
+#include "../../util/header.h"
+
+#define STR_LEN 1024
+#define ID_SIZE 64
+
+static int _get_cpuid(char *buf, size_t sz)
+{
+	const char *sysfs = sysfs__mountpoint();
+	u64 id = 0;
+	char path[PATH_MAX];
+	FILE *file;
+
+	if (!sysfs || sz < ID_SIZE)
+		return -EINVAL;
+
+	scnprintf(path, PATH_MAX, "%s/devices/platform/riscv-pmu/id",
+			sysfs);
+
+	file = fopen(path, "r");
+	if (!file) {
+		pr_debug("fopen failed for file %s\n", path);
+		return -EINVAL;
+	}
+	if (!fgets(buf, ID_SIZE, file)) {
+		fclose(file);
+		return -EINVAL;
+	}
+
+	fclose(file);
+
+	/*Check if value is numeric and remove special characters*/
+	id = strtoul(buf, NULL, 16);
+	if (!id)
+		return -EINVAL;
+	scnprintf(buf, ID_SIZE, "0x%lx", id);
+
+	return 0;
+}
+
+char *get_cpuid_str(struct perf_pmu *pmu __maybe_unused)
+{
+	char *buf = NULL;
+	int res;
+
+	if (!pmu)
+		return NULL;
+
+	buf = malloc(ID_SIZE);
+	if (!buf)
+		return NULL;
+
+	/* read id */
+	res = _get_cpuid(buf, ID_SIZE);
+	if (res) {
+		pr_err("failed to get cpuid string for PMU %s\n", pmu->name);
+		free(buf);
+		buf = NULL;
+	}
+
+	return buf;
+}
-- 
2.35.1

Re: [PATCH v3 2/4] RISC-V: Support CPUID for risc-v in perf

[Will Deacon]

On Tue, Jun 07, 2022 at 04:16:45PM +0300, Nikita Shubin wrote:
> From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> 
> This patch creates the header.c file for the risc-v architecture and introduces support for
> PMU identification through sysfs.
> It is now possible to configure pmu-events in risc-v.
> 
> Depends on patch [1], that introduces the id sysfs file.
> 
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> [Nikita: replaced soc:pmu to riscv-pmu/id]
> Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
> ---
> v2->v3:
> - Change 'soc/soc:pmu/id' to 'riscv-pmu/id'
> ---
>  drivers/perf/riscv_pmu.c            | 18 ++++++++
>  tools/perf/arch/riscv/util/Build    |  1 +
>  tools/perf/arch/riscv/util/header.c | 66 +++++++++++++++++++++++++++++

You will need to separate out the kernel changes from the tooling changes in
order to get this merged.

Thanks,

Will

[PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

[Nikita Shubin]

From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>

The pmu-events now supports custom events for RISC-V, plus the cycle,
time and instret events were defined.

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Tested-by: Nikita Shubin <n.shubin@yadro.com>
---
 tools/perf/pmu-events/arch/riscv/mapfile.csv  | 14 +++++++++++++
 .../pmu-events/arch/riscv/riscv-generic.json  | 20 +++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
 create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json

diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
new file mode 100644
index 000000000000..4f2aa199d9cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+#	MIDR,Version,JSON/file/pathname,Type
+#
+# where
+#	MIDR	Processor version
+#		Variant[23:20] and Revision [3:0] should be zero.
+#	Version could be used to track version of JSON file
+#		but currently unused.
+#	JSON/file/pathname is the path to JSON file, relative
+#		to tools/perf/pmu-events/arch/riscv/.
+#	Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
new file mode 100644
index 000000000000..013e50efad99
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
@@ -0,0 +1,20 @@
+[
+  {
+    "PublicDescription": "CPU Cycles",
+    "EventCode": "0x00",
+    "EventName": "riscv_cycles",
+    "BriefDescription": "CPU cycles RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Time",
+      "EventCode": "0x01",
+      "EventName": "riscv_time",
+      "BriefDescription": "CPU time RISC-V generic counter"
+  },
+  {
+    "PublicDescription": "CPU Instructions",
+      "EventCode": "0x02",
+      "EventName": "riscv_instret",
+      "BriefDescription": "CPU retired instructions RISC-V generic counter"
+  }
+]
\ No newline at end of file
-- 
2.35.1

Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

[John Garry]

On 07/06/2022 14:16, Nikita Shubin wrote:
> From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> 
> The pmu-events now supports custom events for RISC-V, plus the cycle,
> time and instret events were defined.
> 
> Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> Tested-by: Nikita Shubin <n.shubin@yadro.com>
> ---
>   tools/perf/pmu-events/arch/riscv/mapfile.csv  | 14 +++++++++++++
>   .../pmu-events/arch/riscv/riscv-generic.json  | 20 +++++++++++++++++++
>   2 files changed, 34 insertions(+)
>   create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
>   create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-generic.json
> 
> diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> new file mode 100644
> index 000000000000..4f2aa199d9cb
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> @@ -0,0 +1,14 @@
> +# Format:
> +#	MIDR,Version,JSON/file/pathname,Type
> +#
> +# where
> +#	MIDR	Processor version

ARM, no?

> +#		Variant[23:20] and Revision [3:0] should be zero.
> +#	Version could be used to track version of JSON file
> +#		but currently unused.
> +#	JSON/file/pathname is the path to JSON file, relative
> +#		to tools/perf/pmu-events/arch/riscv/.
> +#	Type is core, uncore etc
> +#
> +#
> +#Family-model,Version,Filename,EventType
> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> new file mode 100644
> index 000000000000..013e50efad99
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json

where or how are these referenced?

> @@ -0,0 +1,20 @@
> +[
> +  {
> +    "PublicDescription": "CPU Cycles",
> +    "EventCode": "0x00",
> +    "EventName": "riscv_cycles",
> +    "BriefDescription": "CPU cycles RISC-V generic counter"
> +  },
> +  {
> +    "PublicDescription": "CPU Time",
> +      "EventCode": "0x01",
> +      "EventName": "riscv_time",
> +      "BriefDescription": "CPU time RISC-V generic counter"
> +  },
> +  {
> +    "PublicDescription": "CPU Instructions",
> +      "EventCode": "0x02",
> +      "EventName": "riscv_instret",
> +      "BriefDescription": "CPU retired instructions RISC-V generic counter"
> +  }
> +]
> \ No newline at end of file

Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

[Nikita Shubin]

Hello, John.

On Wed, 8 Jun 2022 11:45:53 +0100
John Garry <john.garry@huawei.com> wrote:

> On 07/06/2022 14:16, Nikita Shubin wrote:
> > From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> > 
> > The pmu-events now supports custom events for RISC-V, plus the
> > cycle, time and instret events were defined.
> > 
> > Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
> > Tested-by: Nikita Shubin <n.shubin@yadro.com>
> > ---
> >   tools/perf/pmu-events/arch/riscv/mapfile.csv  | 14 +++++++++++++
> >   .../pmu-events/arch/riscv/riscv-generic.json  | 20
> > +++++++++++++++++++ 2 files changed, 34 insertions(+)
> >   create mode 100644 tools/perf/pmu-events/arch/riscv/mapfile.csv
> >   create mode 100644
> > tools/perf/pmu-events/arch/riscv/riscv-generic.json
> > 
> > diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > b/tools/perf/pmu-events/arch/riscv/mapfile.csv new file mode 100644
> > index 000000000000..4f2aa199d9cb
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
> > @@ -0,0 +1,14 @@
> > +# Format:
> > +#	MIDR,Version,JSON/file/pathname,Type
> > +#
> > +# where
> > +#	MIDR	Processor version  
> 
> ARM, no?

I've messed with --cc-cmd badly and didn't include every one in cover
letter, sorry for that, attaching link to cover letter:

https://lore.kernel.org/all/20220607131648.29439-1-nikita.shubin@maquefel.me/

They are ARM inspired indeed.


> 
> > +#		Variant[23:20] and Revision [3:0] should be zero.
> > +#	Version could be used to track version of JSON file
> > +#		but currently unused.
> > +#	JSON/file/pathname is the path to JSON file, relative
> > +#		to tools/perf/pmu-events/arch/riscv/.
> > +#	Type is core, uncore etc
> > +#
> > +#
> > +#Family-model,Version,Filename,EventType
> > diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
> > b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
> > 100644 index 000000000000..013e50efad99
> > --- /dev/null
> > +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json  
> 
> where or how are these referenced?

Currently they are not referenced in this version of series at all,
their purpose is to be used like "ArchStdEvent".

Through any RISCV implementation should have at least these 3 events.

Yours,
Nikita Shubin.

> 
> > @@ -0,0 +1,20 @@
> > +[
> > +  {
> > +    "PublicDescription": "CPU Cycles",
> > +    "EventCode": "0x00",
> > +    "EventName": "riscv_cycles",
> > +    "BriefDescription": "CPU cycles RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Time",
> > +      "EventCode": "0x01",
> > +      "EventName": "riscv_time",
> > +      "BriefDescription": "CPU time RISC-V generic counter"
> > +  },
> > +  {
> > +    "PublicDescription": "CPU Instructions",
> > +      "EventCode": "0x02",
> > +      "EventName": "riscv_instret",
> > +      "BriefDescription": "CPU retired instructions RISC-V generic
> > counter"
> > +  }
> > +]
> > \ No newline at end of file  
> 

Re: [PATCH v3 3/4] RISC-V: Added generic pmu-events mapfile

[John Garry]

On 08/06/2022 15:41, Nikita Shubin wrote:
>>> mat:
>>> +#	MIDR,Version,JSON/file/pathname,Type
>>> +#
>>> +# where
>>> +#	MIDR	Processor version
>> ARM, no?

I'm just saying that MIDR is for ARM, so please ensure that this term is 
correct for riscv

> I've messed with --cc-cmd badly and didn't include every one in cover
> letter, sorry for that, attaching link to cover letter:
> 
> https://lore.kernel.org/all/20220607131648.29439-1-nikita.shubin@maquefel.me/
> 
> They are ARM inspired indeed.
> 
> 
>>> +#		Variant[23:20] and Revision [3:0] should be zero.
>>> +#	Version could be used to track version of JSON file
>>> +#		but currently unused.
>>> +#	JSON/file/pathname is the path to JSON file, relative
>>> +#		to tools/perf/pmu-events/arch/riscv/.
>>> +#	Type is core, uncore etc
>>> +#
>>> +#
>>> +#Family-model,Version,Filename,EventType
>>> diff --git a/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>>> b/tools/perf/pmu-events/arch/riscv/riscv-generic.json new file mode
>>> 100644 index 000000000000..013e50efad99
>>> --- /dev/null
>>> +++ b/tools/perf/pmu-events/arch/riscv/riscv-generic.json
>> where or how are these referenced?
> Currently they are not referenced in this version of series at all,

ok, right, so a general kernel policy is not to include code which is 
not referenced.

> their purpose is to be used like "ArchStdEvent".
> 
> Through any RISCV implementation should have at least these 3 events.

Thanks,
John

[PATCH v3 4/4] RISC-V: Added HiFive Unmatched PMU events

[Nikita Shubin]

From: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>

This patch contains all the available events for the HiFive Unmatched performance monitoring unit.

Depends on patch [3], for the base mapfile.csv file.

Signed-off-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Tested-by: Nikita Shubin <n.shubin@yadro.com>
---
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
 .../arch/riscv/sifive/u74/instructions.json   | 92 +++++++++++++++++++
 .../arch/riscv/sifive/u74/memory.json         | 32 +++++++
 .../arch/riscv/sifive/u74/microarch.json      | 57 ++++++++++++
 4 files changed, 182 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json

diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-events/arch/riscv/mapfile.csv
index 4f2aa199d9cb..bda3fb9382f1 100644
--- a/tools/perf/pmu-events/arch/riscv/mapfile.csv
+++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv
@@ -12,3 +12,4 @@
 #
 #
 #Family-model,Version,Filename,EventType
+0x48980072018,v1,sifive/u74,core
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
new file mode 100644
index 000000000000..5eab718c9256
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
@@ -0,0 +1,92 @@
+[
+  {
+    "EventName": "EXCEPTION_TAKEN",
+    "EventCode": "0x0000100",
+    "BriefDescription": "Exception taken"
+  },
+  {
+    "EventName": "INTEGER_LOAD_RETIRED",
+    "EventCode": "0x0000200",
+    "BriefDescription": "Integer load instruction retired"
+  },
+  {
+    "EventName": "INTEGER_STORE_RETIRED",
+    "EventCode": "0x0000400",
+    "BriefDescription": "Integer store instruction retired"
+  },
+  {
+    "EventName": "ATOMIC_MEMORY_RETIRED",
+    "EventCode": "0x0000800",
+    "BriefDescription": "Atomic memory operation retired"
+  },
+  {
+    "EventName": "SYSTEM_INSTRUCTION_RETIRED",
+    "EventCode": "0x0001000",
+    "BriefDescription": "System instruction retired"
+  },
+  {
+    "EventName": "INTEGER_ARITHMETIC_RETIRED",
+    "EventCode": "0x0002000",
+    "BriefDescription": "Integer arithmetic instruction retired"
+  },
+  {
+    "EventName": "CONDITIONAL_BRANCH_RETIRED",
+    "EventCode": "0x0004000",
+    "BriefDescription": "Conditional branch retired"
+  },
+  {
+    "EventName": "JAL_INSTRUCTION_RETIRED",
+    "EventCode": "0x0008000",
+    "BriefDescription": "JAL instruction retired"
+  },
+  {
+    "EventName": "JALR_INSTRUCTION_RETIRED",
+    "EventCode": "0x0010000",
+    "BriefDescription": "JALR instruction retired"
+  },
+  {
+    "EventName": "INTEGER_MULTIPLICATION_RETIRED",
+    "EventCode": "0x0020000",
+    "BriefDescription": "Integer multiplication instruction retired"
+  },
+  {
+    "EventName": "INTEGER_DIVISION_RETIRED",
+    "EventCode": "0x0040000",
+    "BriefDescription": "Integer division instruction retired"
+  },
+  {
+    "EventName": "FP_LOAD_RETIRED",
+    "EventCode": "0x0080000",
+    "BriefDescription": "Floating-point load instruction retired"
+  },
+  {
+    "EventName": "FP_STORE_RETIRED",
+    "EventCode": "0x0100000",
+    "BriefDescription": "Floating-point store instruction retired"
+  },
+  {
+    "EventName": "FP_ADDITION_RETIRED",
+    "EventCode": "0x0200000",
+    "BriefDescription": "Floating-point addition retired"
+  },
+  {
+    "EventName": "FP_MULTIPLICATION_RETIRED",
+    "EventCode": "0x0400000",
+    "BriefDescription": "Floating-point multiplication retired"
+  },
+  {
+    "EventName": "FP_FUSEDMADD_RETIRED",
+    "EventCode": "0x0800000",
+    "BriefDescription": "Floating-point fused multiply-add retired"
+  },
+  {
+    "EventName": "FP_DIV_SQRT_RETIRED",
+    "EventCode": "0x1000000",
+    "BriefDescription": "Floating-point division or square-root retired"
+  },
+  {
+    "EventName": "OTHER_FP_RETIRED",
+    "EventCode": "0x2000000",
+    "BriefDescription": "Other floating-point instruction retired"
+  }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
new file mode 100644
index 000000000000..be1a46312ac3
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
@@ -0,0 +1,32 @@
+[
+  {
+    "EventName": "ICACHE_RETIRED",
+    "EventCode": "0x0000102",
+    "BriefDescription": "Instruction cache miss"
+  },
+  {
+    "EventName": "DCACHE_MISS_MMIO_ACCESSES",
+    "EventCode": "0x0000202",
+    "BriefDescription": "Data cache miss or memory-mapped I/O access"
+  },
+  {
+    "EventName": "DCACHE_WRITEBACK",
+    "EventCode": "0x0000402",
+    "BriefDescription": "Data cache write-back"
+  },
+  {
+    "EventName": "INST_TLB_MISS",
+    "EventCode": "0x0000802",
+    "BriefDescription": "Instruction TLB miss"
+  },
+  {
+    "EventName": "DATA_TLB_MISS",
+    "EventCode": "0x0001002",
+    "BriefDescription": "Data TLB miss"
+  },
+  {
+    "EventName": "UTLB_MISS",
+    "EventCode": "0x0002002",
+    "BriefDescription": "UTLB miss"
+  }
+]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
new file mode 100644
index 000000000000..50ffa55418cb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
@@ -0,0 +1,57 @@
+[
+  {
+    "EventName": "ADDRESSGEN_INTERLOCK",
+    "EventCode": "0x0000101",
+    "BriefDescription": "Address-generation interlock"
+  },
+  {
+    "EventName": "LONGLAT_INTERLOCK",
+    "EventCode": "0x0000201",
+    "BriefDescription": "Long-latency interlock"
+  },
+  {
+    "EventName": "CSR_READ_INTERLOCK",
+    "EventCode": "0x0000401",
+    "BriefDescription": "CSR read interlock"
+  },
+  {
+    "EventName": "ICACHE_ITIM_BUSY",
+    "EventCode": "0x0000801",
+    "BriefDescription": "Instruction cache/ITIM busy"
+  },
+  {
+    "EventName": "DCACHE_DTIM_BUSY",
+    "EventCode": "0x0001001",
+    "BriefDescription": "Data cache/DTIM busy"
+  },
+  {
+    "EventName": "BRANCH_DIRECTION_MISPREDICTION",
+    "EventCode": "0x0002001",
+    "BriefDescription": "Branch direction misprediction"
+  },
+  {
+    "EventName": "BRANCH_TARGET_MISPREDICTION",
+    "EventCode": "0x0004001",
+    "BriefDescription": "Branch/jump target misprediction"
+  },
+  {
+    "EventName": "PIPE_FLUSH_CSR_WRITE",
+    "EventCode": "0x0008001",
+    "BriefDescription": "Pipeline flush from CSR write"
+  },
+  {
+    "EventName": "PIPE_FLUSH_OTHER_EVENT",
+    "EventCode": "0x0010001",
+    "BriefDescription": "Pipeline flush from other event"
+  },
+  {
+    "EventName": "INTEGER_MULTIPLICATION_INTERLOCK",
+    "EventCode": "0x0020001",
+    "BriefDescription": "Integer multiplication interlock"
+  },
+  {
+    "EventName": "FP_INTERLOCK",
+    "EventCode": "0x0040001",
+    "BriefDescription": "Floating-point interlock"
+  }
+]
\ No newline at end of file
-- 
2.35.1