From: Ian Rogers <irogers@google.com>
To: perry.taylor@intel.com, caleb.biggers@intel.com,
kshipra.bopardikar@intel.com,
Kan Liang <kan.liang@linux.intel.com>,
Zhengjun Xing <zhengjun.xing@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Andi Kleen <ak@linux.intel.com>,
James Clark <james.clark@arm.com>,
John Garry <john.garry@huawei.com>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Sedat Dilek <sedat.dilek@gmail.com>
Cc: Stephane Eranian <eranian@google.com>, Ian Rogers <irogers@google.com>
Subject: [PATCH v1 09/31] perf vendor events: Update goldmont mapfile.csv
Date: Fri, 22 Jul 2022 15:32:18 -0700 [thread overview]
Message-ID: <20220722223240.1618013-10-irogers@google.com> (raw)
In-Reply-To: <20220722223240.1618013-1-irogers@google.com>
Align end of file whitespace with what is generated by:
https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py
Modify mapfile.csv to have a missing goldmont cpuid.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/arch/x86/goldmont/cache.json | 2 +-
tools/perf/pmu-events/arch/x86/goldmont/floating-point.json | 2 +-
tools/perf/pmu-events/arch/x86/goldmont/frontend.json | 2 +-
tools/perf/pmu-events/arch/x86/goldmont/memory.json | 2 +-
tools/perf/pmu-events/arch/x86/goldmont/pipeline.json | 2 +-
tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json | 2 +-
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
7 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
index 0b887d73b7f3..ed957d4f9c6d 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json
@@ -1300,4 +1300,4 @@
"SampleAfterValue": "100007",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
index bb364a04a75f..37174392a510 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json
@@ -30,4 +30,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x8"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
index 120ff65897c0..216da6e121c8 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json
@@ -79,4 +79,4 @@
"SampleAfterValue": "200003",
"UMask": "0x1"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
index 6252503f68a1..9f6f0328249e 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json
@@ -31,4 +31,4 @@
"SampleAfterValue": "200003",
"UMask": "0x4"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
index 5dba4313013f..42ff0b134aeb 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
@@ -354,7 +354,7 @@
"Counter": "0,1,2,3",
"EventCode": "0xC3",
"EventName": "MACHINE_CLEARS.SMC",
- "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",
+ "PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel(R) architecture processors.",
"SampleAfterValue": "200003",
"UMask": "0x1"
},
diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
index d5e89c74a9be..2e17e02e1463 100644
--- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
+++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
@@ -75,4 +75,4 @@
"SampleAfterValue": "200003",
"UMask": "0x2"
}
-]
\ No newline at end of file
+]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b105d80d2b7d..ef0beab68a90 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -6,7 +6,7 @@ GenuineIntel-6-56,v23,broadwellde,core
GenuineIntel-6-4F,v19,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.16,cascadelakex,core
GenuineIntel-6-96,v1.03,elkhartlake,core
-GenuineIntel-6-5C,v8,goldmont,core
+GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1,goldmontplus,core
GenuineIntel-6-3C,v24,haswell,core
GenuineIntel-6-45,v24,haswell,core
--
2.37.1.359.gd136c6c3e2-goog
next prev parent reply other threads:[~2022-07-22 22:33 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-22 22:32 [PATCH v1 00/31] Add generated latest Intel events and metrics Ian Rogers
2022-07-22 22:32 ` [PATCH v1 01/31] perf test: Avoid sysfs state affecting fake events Ian Rogers
2022-07-22 22:32 ` [PATCH v1 06/31] perf vendor events: Update bonnell mapfile.csv Ian Rogers
2022-07-22 22:32 ` Ian Rogers [this message]
2022-07-22 22:32 ` [PATCH v1 10/31] perf vendor events: Update goldmontplus mapfile.csv Ian Rogers
2022-07-22 22:32 ` [PATCH v1 11/31] perf vendor events: Update Intel haswell Ian Rogers
2022-07-22 22:32 ` [PATCH v1 13/31] perf vendor events: Update Intel icelake Ian Rogers
2022-07-22 22:32 ` [PATCH v1 14/31] perf vendor events: Update Intel icelakex Ian Rogers
2022-07-22 22:32 ` [PATCH v1 15/31] perf vendor events: Update Intel ivybridge Ian Rogers
2022-07-22 22:32 ` [PATCH v1 19/31] perf vendor events: Add Intel meteorlake Ian Rogers
2022-07-22 22:32 ` [PATCH v1 20/31] perf vendor events: Update Intel nehalemep Ian Rogers
2022-07-22 22:32 ` [PATCH v1 22/31] perf vendor events: Update Intel sandybridge Ian Rogers
2022-07-22 22:32 ` [PATCH v1 24/31] perf vendor events: Update Intel silvermont Ian Rogers
2022-07-22 22:32 ` [PATCH v1 25/31] perf vendor events: Update Intel skylake Ian Rogers
2022-07-22 22:32 ` [PATCH v1 28/31] perf vendor events: Update Intel tigerlake Ian Rogers
2022-07-22 22:32 ` [PATCH v1 29/31] perf vendor events: Update Intel westmereep-dp Ian Rogers
2022-07-22 22:32 ` [PATCH v1 30/31] perf vendor events: Update Intel westmereep-sp Ian Rogers
2022-07-22 22:32 ` [PATCH v1 31/31] perf vendor events: Update Intel westmereex Ian Rogers
2022-07-24 5:51 ` [PATCH v1 00/31] Add generated latest Intel events and metrics Sedat Dilek
2022-07-24 19:08 ` Ian Rogers
2022-07-27 6:48 ` Sedat Dilek
2022-07-27 22:30 ` Ian Rogers
[not found] ` <20220722223240.1618013-3-irogers@google.com>
[not found] ` <2c29ab7e-5fc5-5458-926c-11430e7c3c3b@linux.intel.com>
[not found] ` <CAP-5=fV65fiadnaAmebYS1CjxwuFy4oKxV88v6oHdVPCc=n+Ow@mail.gmail.com>
2022-07-26 1:25 ` [PATCH v1 02/31] perf vendor events: Update Intel broadwellx Xing Zhengjun
2022-07-26 4:49 ` Ian Rogers
2022-07-26 5:19 ` Xing Zhengjun
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