From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3C21C433FE for ; Wed, 19 Oct 2022 19:11:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229786AbiJSTLo (ORCPT ); Wed, 19 Oct 2022 15:11:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50192 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230440AbiJSTLh (ORCPT ); Wed, 19 Oct 2022 15:11:37 -0400 Received: from mail-oi1-f179.google.com (mail-oi1-f179.google.com [209.85.167.179]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 283E71C8D6E; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) Received: by mail-oi1-f179.google.com with SMTP id n83so20327732oif.11; Wed, 19 Oct 2022 12:11:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZBd+XTJESJNOGYoq8Sf5QKUv5aLEk2PWt2aI7lcJy1Q=; b=FH4Jubv70siJQE6Ht/gah9yHhInCnUquqAvEklezWAwx2bc3agYqAqTy6zQmCsQ2Qq 2IF+ZHiuSGc+Bwf2FwctAVeqsJmrLdd8lkQ4tjOn0WTkHVy3jx/CaajdMChgY2y3TV0q JSBNQKmu2fAzESYGRek9T7Quo3vWKx+AwLq9OKD0B+pbpDYPkLTs/+i/MNGF7P7q/3VK z+CrxoMH+KmgtvOY5oIBXcG2l42eh/PjO9SHGkulZotePKtd03KL9B2QHl24RxsMuTgE zLhMj/Wq85d4nUDIpwOwenG7p9n4lgqFjrJs7QWufFY67RPeiqfv/p9FAR+O+xBBEi2H GI2w== X-Gm-Message-State: ACrzQf3mxKBFrp1DiGqHsTD3zZX1VZo4g3c04jfKDZgymb5uZplYCRu9 BT+4jzthoHCHpm1K5rLQaV0v2rMIdQ== X-Google-Smtp-Source: AMsMyM53HC4eCK4NKlfS5OabG/2idCaE/8R5DmuO7iXth8yDJHlcBsw0Hkxwf9ZW/H1vTGzH8KmBcw== X-Received: by 2002:a05:6808:1510:b0:354:566c:78e5 with SMTP id u16-20020a056808151000b00354566c78e5mr19239918oiw.188.1666206691599; Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: from robh_at_kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id q78-20020a4a3351000000b00480db116926sm2048754ooq.27.2022.10.19.12.11.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 19 Oct 2022 12:11:31 -0700 (PDT) Received: (nullmailer pid 3420906 invoked by uid 1000); Wed, 19 Oct 2022 19:11:25 -0000 From: Rob Herring Date: Wed, 19 Oct 2022 14:11:28 -0500 Subject: [PATCH v2 5/7] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220825-arm-spe-v8-7-v2-5-e37322d68ac0@kernel.org> References: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org> To: Namhyung Kim , James Morse , Ingo Molnar , Mark Rutland , Marc Zyngier , Suzuki K Poulose , Will Deacon , Alexandru Elisei , Catalin Marinas , Arnaldo Carvalho de Melo , Peter Zijlstra , Alexander Shishkin , Oliver Upton , Jiri Olsa Cc: kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event. Signed-off-by: Rob Herring --- v2: - Update for v6.1 sysreg generated header changes --- arch/arm64/include/asm/sysreg.h | 2 ++ drivers/perf/arm_spe_pmu.c | 4 +++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index d002dd00e53e..06231e896832 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -242,6 +242,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define PMSEVFR_EL1_RES0_V1P1 \ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define PMSEVFR_EL1_RES0_V1P2 \ + (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..0b9b847919d0 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_IMP: return PMSEVFR_EL1_RES0_IMP; case ID_AA64DFR0_EL1_PMSVer_V1P1: + return PMSEVFR_EL1_RES0_V1P1; + case ID_AA64DFR0_EL1_PMSVer_V1P2: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P1; + return PMSEVFR_EL1_RES0_V1P2; } } -- b4 0.11.0-dev