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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id 9-20020aca0d09000000b00359a9663053sm1570850oin.4.2022.11.04.08.55.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:16 -0700 (PDT) Received: (nullmailer pid 1880407 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 Subject: [PATCH v3 0/8] perf: Arm SPEv1.2 support MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-b4-tracking: H4sIANQ1ZWMC/33NQQ6CMBAF0KuQrh1TpgLFlfcwLko7QCO2ptUmhnB3J+5c6Gryf/L+rCJT8pTFsV pFouKzj4GD2lXCziZMBN5xFigRpcYGTLpBvhMUDR2M5EZ5oLodUQkmg8kEQzLBzozCc1m4nH1+xPT6 vCg1n/OPtVKDBNs1g3Y9Utvj6Uop0LKPaRIXXir4TyNrUp1CdK02Vn7pbdveeUPe4ewAAAA= From: Rob Herring Date: Fri, 04 Nov 2022 10:55:00 -0500 Message-Id: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org This series adds support for Arm SPEv1.2 which is part of the Armv8.7/Armv9.2 architecture. There's 2 new features that affect the kernel: a new event filter bit, branch 'not taken', and an inverted event filter register. Since this support adds new registers and fields, first the SPE register defines are converted to automatic generation. Note that the 'config3' addition in sysfs format files causes SPE to break. A stable fix e552b7be12ed ("perf: Skip and warn on unknown format 'configN' attrs") landed in v6.1-rc1. The perf tool side changes are available here[1]. Tested on FVP. [1] https://lore.kernel.org/all/20220914-arm-perf-tool-spe1-2-v2-v4-0-83c098e6212e@kernel.org/ Signed-off-by: Rob Herring --- Changes in v3: - Add some more missing SPE register fields and use Enums for some fields - Use the new PMSIDR_EL1 register Enum defines in the SPE driver - Link to v2: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v2-0-e37322d68ac0@kernel.org Changes in v2: - Convert the SPE register defines to automatic generation - Fixed access to SYS_PMSNEVFR_EL1 when not present - Rebase on v6.1-rc1 - Link to v1: https://lore.kernel.org/r/20220825-arm-spe-v8-7-v1-0-c75b8d92e692@kernel.org --- Rob Herring (8): perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines arm64: Drop SYS_ from SPE register defines arm64/sysreg: Convert SPE registers to automatic generation perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors perf: arm_spe: Use new PMSIDR_EL1 register enums perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event perf: Add perf_event_attr::config3 perf: arm_spe: Add support for SPEv1.2 inverted event filtering arch/arm64/include/asm/el2_setup.h | 6 +- arch/arm64/include/asm/sysreg.h | 99 +++-------------------- arch/arm64/kvm/debug.c | 2 +- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 +- arch/arm64/tools/sysreg | 139 +++++++++++++++++++++++++++++++++ drivers/perf/arm_spe_pmu.c | 156 ++++++++++++++++++++++++------------- include/uapi/linux/perf_event.h | 3 + 7 files changed, 257 insertions(+), 150 deletions(-) --- base-commit: 9abf2313adc1ca1b6180c508c25f22f9395cc780 change-id: 20220825-arm-spe-v8-7-fedf04e16f23 Best regards, -- Rob Herring