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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id h4-20020a9d2f04000000b00661a3f4113bsm1532860otb.64.2022.11.04.08.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Nov 2022 08:55:27 -0700 (PDT) Received: (nullmailer pid 1880418 invoked by uid 1000); Fri, 04 Nov 2022 15:55:18 -0000 From: Rob Herring Date: Fri, 04 Nov 2022 10:55:05 -0500 Subject: [PATCH v3 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20220825-arm-spe-v8-7-v3-5-87682f78caac@kernel.org> References: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> In-Reply-To: <20220825-arm-spe-v8-7-v3-0-87682f78caac@kernel.org> To: Namhyung Kim , Will Deacon , Arnaldo Carvalho de Melo , Jiri Olsa , Peter Zijlstra , Alexander Shishkin , Mark Rutland , Catalin Marinas , Marc Zyngier , Oliver Upton , Ingo Molnar , Suzuki K Poulose , James Morse , Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, James Clark , Mark Brown , linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu X-Mailer: b4 0.11.0-dev Precedence: bulk List-ID: X-Mailing-List: linux-perf-users@vger.kernel.org Now that the SPE register definitions include enums for some PMSIDR_EL1 fields, use them in the driver in place of magic values. Signed-off-by: Rob Herring --- v3: New patch --- drivers/perf/arm_spe_pmu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9b4bd72087ea..af6d3867c3e7 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -1006,32 +1006,32 @@ static void __arm_spe_pmu_dev_probe(void *info) /* This field has a spaced out encoding, so just use a look-up */ fld = FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { - case 0: + case PMSIDR_EL1_INTERVAL_256: spe_pmu->min_period = 256; break; - case 2: + case PMSIDR_EL1_INTERVAL_512: spe_pmu->min_period = 512; break; - case 3: + case PMSIDR_EL1_INTERVAL_768: spe_pmu->min_period = 768; break; - case 4: + case PMSIDR_EL1_INTERVAL_1024: spe_pmu->min_period = 1024; break; - case 5: + case PMSIDR_EL1_INTERVAL_1536: spe_pmu->min_period = 1536; break; - case 6: + case PMSIDR_EL1_INTERVAL_2048: spe_pmu->min_period = 2048; break; - case 7: + case PMSIDR_EL1_INTERVAL_3072: spe_pmu->min_period = 3072; break; default: dev_warn(dev, "unknown PMSIDR_EL1.Interval [%d]; assuming 8\n", fld); fallthrough; - case 8: + case PMSIDR_EL1_INTERVAL_4096: spe_pmu->min_period = 4096; } @@ -1050,10 +1050,10 @@ static void __arm_spe_pmu_dev_probe(void *info) dev_warn(dev, "unknown PMSIDR_EL1.CountSize [%d]; assuming 2\n", fld); fallthrough; - case 2: + case PMSIDR_EL1_COUNTSIZE_12_BIT_SAT: spe_pmu->counter_sz = 12; break; - case 3: + case PMSIDR_EL1_COUNTSIZE_16_BIT_SAT: spe_pmu->counter_sz = 16; } -- b4 0.11.0-dev